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* Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-183-468/+55
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* Added synth_xilinx -retime -flattenClifford Wolf2015-01-171-2/+28
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* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-174-2/+106
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* Added cells.libClifford Wolf2015-01-162-0/+109
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* Added dff2dffe to synth_xilinxClifford Wolf2015-01-161-0/+2
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* Added more FF types to xilinx/cells.vClifford Wolf2015-01-161-25/+28
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* Fixed xilinx bram clock inverted configClifford Wolf2015-01-161-21/+35
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* Added FF cells to xilinx/cells_sim.vClifford Wolf2015-01-161-116/+116
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* Added Xilinx MUXF7 and MUXF8 supportClifford Wolf2015-01-152-2/+30
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* Various cleanups in synth_xilinx commandClifford Wolf2015-01-131-54/+8
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* Added add_share_file Makefile macroClifford Wolf2015-01-082-38/+10
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* added minimalistic xilinx sim modelsClifford Wolf2015-01-081-0/+150
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* More Xilinx bram cleanupsClifford Wolf2015-01-071-14/+14
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* Cleanups in xilinx bram descriptionsClifford Wolf2015-01-072-36/+36
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* Xilinx RAMB36/RAMB18 memory_bram support completeClifford Wolf2015-01-063-16/+320
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* Towards Xilinx bram supportClifford Wolf2015-01-063-24/+65
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* small fix in xilinx/brams.vClifford Wolf2015-01-061-5/+5
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* Towards Xilinx bram supportClifford Wolf2015-01-064-25/+176
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* Various small improvements to synth_xilinxClifford Wolf2015-01-061-8/+6
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* Towards Xilinx bram supportClifford Wolf2015-01-062-13/+41
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* Towards Xilinx bram supportClifford Wolf2015-01-063-6/+10
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* Towards Xilinx bram supportClifford Wolf2015-01-057-19/+172
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* Towards Xilinx bram supportClifford Wolf2015-01-043-13/+182
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* Progress in memory_bramClifford Wolf2015-01-031-0/+3
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* Added proper clkpol support to memory_bramClifford Wolf2015-01-021-1/+1
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* New $mem simlib modelClifford Wolf2015-01-021-95/+36
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* Progress in memory_bramClifford Wolf2014-12-311-3/+3
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* Added memory_bram (not functional yet)Clifford Wolf2014-12-311-0/+20
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* Fixed simlib entries for $memrd and $memwrClifford Wolf2014-12-301-0/+2
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* Fixed build with SMALL=1Clifford Wolf2014-12-301-0/+2
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* Improvements in simplemap api, added $ne $nex $eq $eqx supportClifford Wolf2014-12-241-49/+5
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* Removed UTF-8 chars from techmap.vClifford Wolf2014-12-121-1/+1
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* Added $dffe cell typeClifford Wolf2014-12-082-1/+20
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* Added $_DFFE_??_ cell typesClifford Wolf2014-12-081-0/+32
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* Added "abc" label in synth scriptClifford Wolf2014-10-311-6/+12
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* Added "opt -full" alias for all more aggressive optimizationsClifford Wolf2014-10-311-2/+6
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* Added $_BUF_ cell typeClifford Wolf2014-10-031-0/+6
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* namespace YosysClifford Wolf2014-09-272-2/+10
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* Improvements in "synth" scriptClifford Wolf2014-09-181-8/+12
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* Fixed $macc simlib model for zero-configClifford Wolf2014-09-161-1/+1
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* Added "synth" commandClifford Wolf2014-09-142-0/+154
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* Using alumacc in techmap.vClifford Wolf2014-09-141-237/+33
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* Fixed simlib $macc model for xilinx xsimClifford Wolf2014-09-081-1/+15
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* Simplified $fa undef modelClifford Wolf2014-09-081-1/+1
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* Fixes and cleanups for blackbox.vClifford Wolf2014-09-082-70/+73
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* Added $lcu cell typeClifford Wolf2014-09-082-74/+31
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* Added "$fa" cell typeClifford Wolf2014-09-082-0/+28
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* Using maccmap for $macc and $mul techmapClifford Wolf2014-09-071-190/+16
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* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-062-2/+2
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* Added $macc SAT modelClifford Wolf2014-09-062-6/+6
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