aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Collapse)AuthorAgeFilesLines
* Improvements in sf2 cells_sim.vClifford Wolf2019-03-062-30/+251
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add sf2 techmap rules for more FF typesClifford Wolf2019-03-061-25/+39
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor SF2 iobuf insertion, Add clkint insertionClifford Wolf2019-03-063-83/+152
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improvements in SF2 flow and demoClifford Wolf2019-03-052-8/+23
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-0510-176/+570
|\ | | | | Changes required for VPR place and route in synth_xilinx
| * Revert BRAM WRITE_MODE changes.Keith Rothman2019-03-041-12/+12
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Revert FF models to include IS_x_INVERTED parameters.Keith Rothman2019-03-011-6/+34
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-011-13/+13
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Modify arguments to match existing style.Keith Rothman2019-03-011-6/+6
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-0111-221/+587
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #850 from daveshah1/ecp5_warn_conflictClifford Wolf2019-03-051-2/+7
|\ \ | | | | | | ecp5: Demote conflicting FF init values to a warning
| * | ecp5: Demote conflicting FF init values to a warningDavid Shah2019-03-041-2/+7
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* / Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix ECP5 cells_sim for iverilogMiodrag Milanovic2019-03-011-2/+3
|
* Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_modeClifford Wolf2019-02-281-2/+2
|\ | | | | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
| * ice40: use 2 bits for READ/WRITE MODE for SB_RAM mapElms2019-02-281-2/+2
| | | | | | | | | | | | EBLIF output .param will only use necessary 2 bits Signed-off-by: Elms <elms@freshred.net>
* | Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-286-19/+19
| |
* | Merge pull request #794 from daveshah1/ecp5improveClifford Wolf2019-02-287-12/+388
|\ \ | |/ |/| ECP5 Improvements
| * ecp5: Compatibility with Migen AsyncResetSynchronizerDavid Shah2019-02-252-0/+20
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * ecp5: Add DDRDLLADavid Shah2019-02-191-0/+9
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * ecp5: Add DELAYF/DELAYG blackboxesDavid Shah2019-02-191-0/+18
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * ecp5: Add ECLKSYNCB blackboxDavid Shah2019-02-131-1/+7
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Full set of IO-related blackboxesDavid Shah2019-02-121-0/+102
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Support for flipflop initialisationDavid Shah2019-01-223-4/+199
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Add LSRMODE to flipflops for PRLD supportDavid Shah2019-01-211-7/+16
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: More blackboxesDavid Shah2019-01-211-0/+17
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Increase threshold for ALU mappingDavid Shah2019-01-211-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut moduleLarry Doolittle2019-02-261-22/+22
| |
* | Clean up some whitepsace outliersLarry Doolittle2019-02-261-2/+2
| |
* | Merge pull request #740 from daveshah1/improve_dressClifford Wolf2019-02-222-3/+3
|\ \ | | | | | | Improve ABC netname preservation
| * | ecp5: Use abc -dressDavid Shah2019-02-061-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ice40: Use abc -dress in synth_ice40David Shah2019-02-061-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | | Bugfix in ice40_dspClifford Wolf2019-02-212-20/+33
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add ice40 test_dsp_map test case generatorClifford Wolf2019-02-202-0/+99
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add "synth_ice40 -dsp"Clifford Wolf2019-02-201-3/+27
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Improve iCE40 SB_MAC16 modelClifford Wolf2019-02-205-121/+179
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add first draft of functional SB_MAC16 modelClifford Wolf2019-02-194-53/+467
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
|/
* Add SF2 IO buffer insertionClifford Wolf2019-01-174-1/+168
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth_sf2 -vlog", fix "synth_sf2 -edif"Clifford Wolf2019-01-171-2/+17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #777 from mmicko/achronix_cell_sim_fixClifford Wolf2019-01-041-1/+1
|\ | | | | Fix cells_sim.v for Achronix FPGA
| * Fix cells_sim.v for Achronix FPGAMiodrag Milanovic2019-01-041-1/+1
| |
* | Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-044-8/+16
|/
* Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-026-2/+96
|\ | | | | anlogic: implement DRAM initialization
| * anlogic: implement DRAM initializationIcenowy Zheng2018-12-206-2/+96
| | | | | | | | | | | | | | | | | | | | | | As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-022-14/+15
|\ \ | | | | | | Initialization of Anlogic DFFs
| * | anlogic: set the init value of DFFsIcenowy Zheng2018-12-182-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As dffinit has already supported for different initialization strings for DFFs and check for re-initialization, initialization of Anlogic DFFs are now ready to go. Support for set the init values of Anlogic DFFs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | | Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-022-7/+41
|\ \ \ | | | | | | | | synth: add k-LUT mode
| * | | synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
| | | |
| * | | synth: add k-LUT mode.whitequark2019-01-021-2/+36
| | | |
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-23 03:00:04 +0000