| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | Use singular for disabling of DRAM or BRAM inference. | Keith Rothman | 2019-03-01 | 1 | -13/+13 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | | * | | Modify arguments to match existing style. | Keith Rothman | 2019-03-01 | 1 | -6/+6 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | | * | | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 11 | -221/+587 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | | | Merge pull request #850 from daveshah1/ecp5_warn_conflict | Clifford Wolf | 2019-03-05 | 1 | -2/+7 | |
| | |\ \ \ | | | | | | | | | | | ecp5: Demote conflicting FF init values to a warning | |||||
| | | * | | | ecp5: Demote conflicting FF init values to a warning | David Shah | 2019-03-04 | 1 | -2/+7 | |
| | | |/ / | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * / / | Use "write_edif -pvector bra" for Xilinx EDIF files | Clifford Wolf | 2019-03-05 | 1 | -1/+1 | |
| | |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Fix ECP5 cells_sim for iverilog | Miodrag Milanovic | 2019-03-01 | 1 | -2/+3 | |
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| | * | | Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode | Clifford Wolf | 2019-02-28 | 1 | -2/+2 | |
| | |\ \ | | | | | | | | | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map | |||||
| | | * | | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map | Elms | 2019-02-28 | 1 | -2/+2 | |
| | | |/ | | | | | | | | | | | | | | | | EBLIF output .param will only use necessary 2 bits Signed-off-by: Elms <elms@freshred.net> | |||||
| | * | | Reduce amount of trailing whitespace in code base | Larry Doolittle | 2019-02-28 | 6 | -19/+19 | |
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| | * | | Merge pull request #794 from daveshah1/ecp5improve | Clifford Wolf | 2019-02-28 | 7 | -12/+388 | |
| | |\ \ | | |/ | |/| | ECP5 Improvements | |||||
| | | * | ecp5: Compatibility with Migen AsyncResetSynchronizer | David Shah | 2019-02-25 | 2 | -0/+20 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| | | * | ecp5: Add DDRDLLA | David Shah | 2019-02-19 | 1 | -0/+9 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| | | * | ecp5: Add DELAYF/DELAYG blackboxes | David Shah | 2019-02-19 | 1 | -0/+18 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| | | * | ecp5: Add ECLKSYNCB blackbox | David Shah | 2019-02-13 | 1 | -1/+7 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | ecp5: Full set of IO-related blackboxes | David Shah | 2019-02-12 | 1 | -0/+102 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | ecp5: Support for flipflop initialisation | David Shah | 2019-01-22 | 3 | -4/+199 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | ecp5: Add LSRMODE to flipflops for PRLD support | David Shah | 2019-01-21 | 1 | -7/+16 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | ecp5: More blackboxes | David Shah | 2019-01-21 | 1 | -0/+17 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | ecp5: Increase threshold for ALU mapping | David Shah | 2019-01-21 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module | Larry Doolittle | 2019-02-26 | 1 | -22/+22 | |
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| | * | | Clean up some whitepsace outliers | Larry Doolittle | 2019-02-26 | 1 | -2/+2 | |
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| * | | | Add shregmap -init_msb_first and use in synth_xilinx | Eddie Hung | 2019-03-14 | 1 | -2/+2 | |
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| * | | | Fix cells_map for SRL | Eddie Hung | 2019-03-14 | 1 | -19/+17 | |
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| * | | | Move shregmap until after first techmap | Eddie Hung | 2019-03-13 | 1 | -2/+2 | |
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| * | | | Refactor $__SHREG__ in cells_map.v | Eddie Hung | 2019-03-13 | 1 | -32/+24 | |
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| * | | | Remove SRL16/32 from cells_xtra | Eddie Hung | 2019-02-28 | 2 | -18/+2 | |
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| * | | | Add SRL16 and SRL32 sim models | Eddie Hung | 2019-02-28 | 1 | -0/+39 | |
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| * | | | Fix SRL16/32 techmap off-by-one | Eddie Hung | 2019-02-28 | 1 | -18/+24 | |
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| * | | | synth_xilinx to call shregmap with enable support | Eddie Hung | 2019-02-28 | 2 | -24/+29 | |
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| * | | | synth_xilinx to use shregmap with -params too | Eddie Hung | 2019-02-28 | 2 | -22/+19 | |
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| * | | | synth_xilinx to now have shregmap call after dff2dffe | Eddie Hung | 2019-02-28 | 1 | -0/+2 | |
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| * | | | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32 | Eddie Hung | 2019-02-28 | 1 | -0/+71 | |
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| * | | Merge pull request #740 from daveshah1/improve_dress | Clifford Wolf | 2019-02-22 | 2 | -3/+3 | |
| |\ \ | | | | | | | Improve ABC netname preservation | |||||
| | * | | ecp5: Use abc -dress | David Shah | 2019-02-06 | 1 | -2/+2 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| | * | | ice40: Use abc -dress in synth_ice40 | David Shah | 2019-02-06 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | Bugfix in ice40_dsp | Clifford Wolf | 2019-02-21 | 2 | -20/+33 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add ice40 test_dsp_map test case generator | Clifford Wolf | 2019-02-20 | 2 | -0/+99 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "synth_ice40 -dsp" | Clifford Wolf | 2019-02-20 | 1 | -3/+27 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Improve iCE40 SB_MAC16 model | Clifford Wolf | 2019-02-20 | 5 | -121/+179 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add first draft of functional SB_MAC16 model | Clifford Wolf | 2019-02-19 | 4 | -53/+467 | |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * / | Fixed Anlogic simulation model | Miodrag Milanovic | 2019-01-25 | 1 | -1/+1 | |
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| * | Add SF2 IO buffer insertion | Clifford Wolf | 2019-01-17 | 4 | -1/+168 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "synth_sf2 -vlog", fix "synth_sf2 -edif" | Clifford Wolf | 2019-01-17 | 1 | -2/+17 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Merge pull request #777 from mmicko/achronix_cell_sim_fix | Clifford Wolf | 2019-01-04 | 1 | -1/+1 | |
| |\ | | | | | Fix cells_sim.v for Achronix FPGA | |||||
| | * | Fix cells_sim.v for Achronix FPGA | Miodrag Milanovic | 2019-01-04 | 1 | -1/+1 | |
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| * | | Unify usage of noflatten among architectures | Miodrag Milanovic | 2019-01-04 | 4 | -8/+16 | |
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| * | Merge pull request #755 from Icenowy/anlogic-dram-init | Clifford Wolf | 2019-01-02 | 6 | -2/+96 | |
| |\ | | | | | anlogic: implement DRAM initialization | |||||
| | * | anlogic: implement DRAM initialization | Icenowy Zheng | 2018-12-20 | 6 | -2/+96 | |
| | | | | | | | | | | | | | | | | | | | | | | | As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> | |||||
| * | | Merge pull request #750 from Icenowy/anlogic-ff-init | Clifford Wolf | 2019-01-02 | 2 | -14/+15 | |
| |\ \ | | | | | | | Initialization of Anlogic DFFs | |||||
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index : iCE40/yosys | |
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