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| * | | | | ecp5: Pass -nomfs to abc9David Shah2019-10-201-2/+2
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logmsg'> Signed-off-by: David Shah <dave@ds0.me> | | * | | ecp5: Add attrmvcp to copy syn_useioff to driving FFDavid Shah2019-10-101-0/+1 | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | | * | | ecp5: Set syn_useioff on IO FFs to enable packingDavid Shah2019-10-101-8/+8 | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | | * | | xilinx: Add simulation model for IBUFG.Marcin Koƛcielnicki2019-10-105-33/+14 | | | | | | * | | | FF should be initialized to 0Miodrag Milanovic2019-10-041-1/+3 | | | | | | * | | | Add missing latch mappingMiodrag Milanovic2019-10-041-0/+12 | | | | | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-081-5/+9 |\ \ \ \ \ | | |/ / / | |/| | | | * | | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-0831-228/+236 | |\ \ \ \ | | | | | | | | | | | | Rename abc_* names/attributes to more precisely be abc9_* | | * \ \ \ Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-044-181/+9 | | |\ \ \ \ | * | | | | | Add comment on why partial multipliers are 18x18Eddie Hung2019-10-041-4/+8 | | | | | | | | * | | | | | Fix typo in check_label()Eddie Hung2019-10-041-1/+1 | | |/ / / / | |/| | | | * | | | | | CleanupEddie Hung2019-10-071-7/+2 | | | | | | * | | | | | Rename $currQ to $abc9_currQEddie Hung2019-10-071-46/+46 | | | | | | * | | | | | Update comments in abc9_map.vEddie Hung2019-10-071-131/+57 | | | | | | * | | | | | Remove -D_ABC9Eddie Hung2019-10-071-2/+0 | | | | | | * | | | | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-054-230/+200 | | | | | | * | | | | | abc -> abc9Eddie Hung2019-10-041-3/+3 | | | | | | * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-044-181/+9 |\| | | | | | * | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-2/+6 | | | | | | | * | | | | Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2 | | | | | | * | | | | | Use read_args for read_verilogEddie Hung2019-10-041-3/+6 | | | | | | * | | | | | Fix merge issuesEddie Hung2019-10-042-9/+10 | | | | | | * | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-0431-278/+294 |\ \ \ \ \ \ | | |/ / / / | |/| | | | | * | | | | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0431-227/+235 | |/ / / / | * | | | Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-045-31/+4 | | | | | | * | | | OopsEddie Hung2019-10-041-1/+1 | | | | | | * | | | Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29 | |/ / / * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-036-2/+184 |\| | | | * | | ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2 | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | * | | ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183 | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> * | | | EnglishEddie Hung2019-10-031-3/+3 | | | | * | | | More fixesEddie Hung2019-10-011-16/+16 | | | | * | | | Escape Verilog identifiers for legality outside of YosysEddie Hung2019-10-011-48/+48 | | | | * | | | Remove need for $currQ port connectionEddie Hung2019-09-302-111/+118 | | | | * | | | Add explanation to abc_map.vEddie Hung2019-09-301-0/+16 | | | | * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-308-124/+122 |\| | | | * | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46 | | | | | * | | synth_xilinx: Support latches, remove used-up FF init values.Marcin Koƛcielnicki2019-09-302-2/+76 | | | | | | | | | | | | | | | | Fixes #1387. * | | | Missing endmoduleEddie Hung2019-09-291-0/+1 | | | | * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-2919-31/+3401 |\| | | | * | | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2919-31/+3395 | |\ \ \ | | | | | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5) | | * | | Re-orderEddie Hung2019-09-272-2/+2 | | | | | | | * | | Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2 | | | | | | | * | | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run onceEddie Hung2019-09-261-9/+4 | | | | | | | * | | TypoEddie Hung2019-09-261-1/+1 | | | | | | | * | | select onceEddie Hung2019-09-262-8/+12 | | | | | | | * | | Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-263-38/+14 | | | | |