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authorEddie Hung <eddie@fpgeh.com>2019-09-27 14:32:07 -0700
committerEddie Hung <eddie@fpgeh.com>2019-09-27 14:32:07 -0700
commitb3d8a60cbd94176076f23c4ea6c94ec24e6773e0 (patch)
tree31c703711f905d1e5ddd40aa6800cc940a7fccbb /techlibs
parent90236025b7e1409027550451abe4ffc1cc63f128 (diff)
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Re-order
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/ice40/synth_ice40.cc2
-rw-r--r--techlibs/xilinx/synth_xilinx.cc2
2 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 52e13bdc2..841f10244 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -277,9 +277,9 @@ struct SynthIce40Pass : public ScriptPass
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
run("select a:mul2dsp", " (if -dsp)");
+ run("setattr -unset mul2dsp", " (if -dsp)");
run("opt_expr -fine", " (if -dsp)");
run("wreduce", " (if -dsp)");
- run("setattr -unset mul2dsp", " (if -dsp)");
run("select -clear", " (if -dsp)");
run("ice40_dsp", " (if -dsp)");
run("chtype -set $mul t:$__soft_mul", "(if -dsp)");
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d73cc3b16..6c58e0913 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -347,9 +347,9 @@ struct SynthXilinxPass : public ScriptPass
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
run("select a:mul2dsp");
+ run("setattr -unset mul2dsp");
run("opt_expr -fine");
run("wreduce");
- run("setattr -unset mul2dsp");
run("select -clear");
run("xilinx_dsp");
run("chtype -set $mul t:$__soft_mul");