| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | | * | | | | | | | | | | | | | | | | | | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 2 | -111/+118 | |
| | | * | | | | | | | | | | | | | | | | | | | Add explanation to abc_map.v | Eddie Hung | 2019-09-30 | 1 | -0/+16 | |
| | | * | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 8 | -124/+122 | |
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| | | * | | | | | | | | | | | | | | | | | | | | Missing endmodule | Eddie Hung | 2019-09-29 | 1 | -0/+1 | |
| | | * | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 19 | -31/+3401 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | FDCE_1 does not have IS_CLR_INVERTED | Eddie Hung | 2019-09-29 | 1 | -1/+1 | |
| | | * | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -1/+1 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 6 | -295/+314 | |
| | | * | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-27 | 57 | -1594/+22196 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | Revert "Remove sequential extension" | Eddie Hung | 2019-08-20 | 6 | -17/+359 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | Fix DSP48E1 sim | Eddie Hung | 2020-01-06 | 1 | -3/+3 | |
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| * / | | | | | | | | | | | | | | | | | | | | | | | Re-enable &mfs for synth_{ecp5,xilinx} | Eddie Hung | 2020-01-06 | 2 | -3/+2 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1617 from YosysHQ/eddie/abc9_dsp_refactor | Eddie Hung | 2020-01-06 | 5 | -1653/+507 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | Wrap arrival functions inside `YOSYS too | Eddie Hung | 2020-01-06 | 1 | -0/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Fix return value of arrival time functions, fix word | Eddie Hung | 2020-01-06 | 1 | -18/+14 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Drive $[ABCD] explicitly | Eddie Hung | 2020-01-02 | 1 | -15/+21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor | Eddie Hung | 2020-01-02 | 13 | -43/+43 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | ifndef __ICARUS__ -> ifdef YOSYS | Eddie Hung | 2020-01-01 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Rework abc9's DSP48E1 model | Eddie Hung | 2020-01-01 | 5 | -1656/+506 | |
| * | | | | | | | | | | | | | | | | | | | | | | | Valid to have attribute starting with SB_CARRY. | Miodrag Milanovic | 2020-01-04 | 1 | -0/+2 | |
| * | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1604 from whitequark/unify-ram-naming | whitequark | 2020-01-02 | 18 | -40/+67 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys. | whitequark | 2020-01-01 | 18 | -40/+67 | |
| * | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1601 from YosysHQ/eddie/synth_retime | Eddie Hung | 2020-01-02 | 12 | -37/+37 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | Update doc that "-retime" calls abc with "-dff -D 1" | Eddie Hung | 2019-12-30 | 11 | -12/+12 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | Disable synth_gowin -abc9 as it offers no advantages yet | Eddie Hung | 2019-12-30 | 1 | -12/+12 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" | Eddie Hung | 2019-12-30 | 11 | -13/+13 | |
| * | | | | | | | | | | | | | | | | | | | | | | | | ifdef __ICARUS__ -> ifndef YOSYS | Eddie Hung | 2020-01-01 | 1 | -6/+6 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Fix anlogic async flop mapping | Eddie Hung | 2020-01-01 | 1 | -8/+8 | |
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| * | | | | | | | | | | | | | | | | | | | | | | Update timings for Xilinx S7 cells | Eddie Hung | 2019-12-30 | 1 | -15/+35 | |
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| * | | | | | | | | | | | | | | | | | | | | | Merge pull request #1589 from YosysHQ/iopad_default | Miodrag Milanović | 2019-12-30 | 1 | -11/+6 | |
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| | * | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into iopad_default | Miodrag Milanovic | 2019-12-28 | 8 | -10/+368 | |
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| | * | | | | | | | | | | | | | | | | | | | | Addressed review comments | Miodrag Milanovic | 2019-12-21 | 1 | -2/+3 | |
| | * | | | | | | | | | | | | | | | | | | | | iopad no op for compatibility with old scripts | Miodrag Milanovic | 2019-12-21 | 1 | -0/+3 | |
| | * | | | | | | | | | | | | | | | | | | | | Make iopad option default for all xilinx flows | Miodrag Milanovic | 2019-12-21 | 1 | -14/+5 | |
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| * | | | | | | | | | | | | | | | | | | | | Nitpick cleanup for ecp5 | Eddie Hung | 2019-12-27 | 2 | -11/+3 | |
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| * | | | | | | | | | | | | | | | | | | | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen | Marcin Kościelnicki | 2019-12-25 | 3 | -3/+6 | |
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| | * | | | | | | | | | | | | | | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support. | Marcin Kościelnicki | 2019-12-22 | 3 | -3/+6 | |
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| * / / / / / / / / / / / / / / / / / / | xilinx: Test our DSP48A/DSP48A1 simulation models. | Marcin Kościelnicki | 2019-12-23 | 5 | -7/+362 | |
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| * | | | | | | | | | | | | | | | | / | Add abc9_arrival times for RAM{32,64}M | Eddie Hung | 2019-12-20 | 1 | -24/+10 | |
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| * | | | | | | | | | | | | | | | | | Add RAM{32,64}M to abc9_map.v | Eddie Hung | 2019-12-20 | 1 | -0/+78 | |
| * | | | | | | | | | | | | | | | | | Revert "Optimise write_xaiger" | Eddie Hung | 2019-12-20 | 3 | -15/+0 | |
| * | | | | | | | | | | | | | | | | | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-19 | 3 | -0/+15 | |
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| | * | | | | | | | | | | | | | | | | | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger | Eddie Hung | 2019-12-06 | 3 | -0/+15 | |
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| * | | | | | | | | | | | | | | | | | xilinx: Add simulation models for remaining CLB primitives. | Marcin Kościelnicki | 2019-12-19 | 3 | -156/+210 | |
| * | | | | | | | | | | | | | | | | | xilinx_dffopt: Keep order of LUT inputs. | Marcin Kościelnicki | 2019-12-19 | 1 | -16/+30 | |
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| * | | | | | | | | | | | | | | | | Merge pull request #1563 from YosysHQ/dave/async-prld | David Shah | 2019-12-18 | 2 | -4/+28 | |
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| | * | | | | | | | | | | | | | | | | ecp5: Add support for mapping PRLD FFs | David Shah | 2019-12-07 | 2 | -4/+28 | |
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| * | | | | | | | | | | | | | | | | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 6 | -22/+389 | |
| * | | | | | | | | | | | | | | | | xilinx: Improve flip-flop handling. | Marcin Kościelnicki | 2019-12-18 | 4 | -38/+228 | |
| * | | | | | | | | | | | | | | | | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram | Eddie Hung | 2019-12-16 | 3 | -12/+301 | |
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index : iCE40/yosys | |
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