| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Fix indentation in `techlibs/ice40/synth_ice40.cc`. | Alberto Gonzalez | 2020-04-01 | 1 | -4/+4 |
| * | Merge pull request #1794 from YosysHQ/dave/mince-abc9-fix | David Shah | 2020-03-21 | 1 | -0/+1 |
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| | * | ice40: Map unmapped 'mince' DFFs to gate level | David Shah | 2020-03-20 | 1 | -0/+1 |
| * | | ice40: Fix typos in SPRAM ABC9 timing specs | Sylvain Munaut | 2020-03-20 | 1 | -2/+2 |
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| * | xilinx: Mark IOBUFDS.IOB as external pad | Marcin Kościelnicki | 2020-03-20 | 2 | -1/+2 |
| * | ice40: Fix SPRAM model to keep data stable if chipselect is low | Sylvain Munaut | 2020-03-14 | 1 | -5/+8 |
| * | Fix invalid verilog syntax | Miodrag Milanovic | 2020-03-14 | 1 | -1/+1 |
| * | Merge pull request #1716 from zeldin/ecp5_fix | N. Engelhardt | 2020-03-09 | 1 | -2/+0 |
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| | * | remove unused parameters | N. Engelhardt | 2020-03-06 | 1 | -3/+0 |
| | * | ecp5: Add missing parameter to \$__ECP5_PDPW16KD | Marcus Comstedt | 2020-02-22 | 1 | -0/+1 |
| * | | ice40: fix specify for ICE40_{LP,U} | Eddie Hung | 2020-03-05 | 1 | -4/+4 |
| * | | ice40: fix implicit signal in specify, also clamp negative times to 0 | Eddie Hung | 2020-03-04 | 1 | -22/+22 |
| * | | Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1 | Eddie Hung | 2020-03-04 | 4 | -109/+244 |
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| | * | | xilinx: consider DSP48E1.ADREG | Eddie Hung | 2020-03-04 | 4 | -5/+8 |
| | * | | xilinx: cleanup DSP48E1 handling for abc9 | Eddie Hung | 2020-03-04 | 3 | -86/+125 |
| | * | | xilinx: improve specify for DSP48E1 | Eddie Hung | 2020-03-04 | 1 | -32/+116 |
| | * | | xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v | Eddie Hung | 2020-03-04 | 2 | -5/+14 |
| * | | | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc | N. Engelhardt | 2020-03-03 | 2 | -6/+39 |
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| | * | | Add -flowmap to synth and synth_ice40 | Dan Ravensloft | 2020-02-28 | 2 | -6/+39 |
| * | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specify | Eddie Hung | 2020-03-02 | 30 | -1440/+2803 |
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| | * | | | Remove RAMB{18,36}E1 from cells_xtra.py | Eddie Hung | 2020-02-27 | 1 | -2/+2 |
| | * | | | xilinx: Update RAMB* specify entries | Eddie Hung | 2020-02-27 | 1 | -11/+42 |
| | * | | | ice40: add delays to SB_CARRY | Eddie Hung | 2020-02-27 | 1 | -0/+30 |
| | * | | | xilinx: add delays to INV | Eddie Hung | 2020-02-27 | 1 | -0/+3 |
| | * | | | More +/ice40/cells_sim.v fixes | Eddie Hung | 2020-02-27 | 1 | -27/+27 |
| | * | | | Make +/xilinx/cells_sim.v legal | Eddie Hung | 2020-02-27 | 1 | -76/+78 |
| | * | | | Get rid of (* abc9_{arrival,required} *) entirely | Eddie Hung | 2020-02-27 | 3 | -530/+496 |
| | * | | | abc9_ops: use TimingInfo for -prep_{lut,box} too | Eddie Hung | 2020-02-27 | 1 | -7/+10 |
| | * | | | Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy | Eddie Hung | 2020-02-27 | 1 | -14/+12 |
| | * | | | ice40: fix specify for inverted clocks | Eddie Hung | 2020-02-27 | 1 | -27/+27 |
| | * | | | Fix tests by gating some specify constructs from iverilog | Eddie Hung | 2020-02-27 | 1 | -0/+16 |
| | * | | | abc9_ops: ignore (* abc9_flop *) if not '-dff' | Eddie Hung | 2020-02-27 | 1 | -2/+6 |
| | * | | | ice40: specify fixes | Eddie Hung | 2020-02-27 | 3 | -66/+66 |
| | * | | | ice40: move over to specify blocks for -abc9 | Eddie Hung | 2020-02-27 | 10 | -164/+1344 |
| | * | | | synth_ecp5: use +/abc9_model.v | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
| | * | | | Update xilinx for ABC9 | Eddie Hung | 2020-02-27 | 3 | -20/+16 |
| | * | | | Create +/abc9_model.v for $__ABC9_{DELAY,FF_} | Eddie Hung | 2020-02-27 | 2 | -0/+11 |
| | * | | | ecp5: remove small LUT entries | Eddie Hung | 2020-02-27 | 1 | -24/+6 |
| | * | | | Fix commented out specify statement | Eddie Hung | 2020-02-27 | 1 | -6/+6 |
| | * | | | xilinx: improve specify functionality | Eddie Hung | 2020-02-27 | 5 | -446/+519 |
| | * | | | ecp5: deprecate abc9_{arrival,required} and *.{lut,box} | Eddie Hung | 2020-02-27 | 7 | -86/+120 |
| | * | | | xilinx: use specify blocks in place of abc9_{arrival,required} | Eddie Hung | 2020-02-27 | 1 | -176/+404 |
| | * | | | Auto-generate .box/.lut files from specify blocks | Eddie Hung | 2020-02-27 | 7 | -426/+151 |
| | * | | | abc9_ops: -prep_box, to be called once | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
| | * | | | abc9_ops: -prep_lut and -write_lut to auto-generate LUT library | Eddie Hung | 2020-02-27 | 2 | -4/+85 |
| * | | | | coolrunner2: Attempt to give wires/cells more meaningful names | R. Ou | 2020-03-02 | 2 | -23/+66 |
| * | | | | coolrunner2: Fix invalid multiple fanouts of XOR/OR gates | R. Ou | 2020-03-02 | 1 | -0/+96 |
| * | | | | coolrunner2: Fix packed register+input buffer insertion | R. Ou | 2020-03-02 | 1 | -2/+84 |
| * | | | | coolrunner2: Insert many more required feedthrough cells | R. Ou | 2020-03-01 | 3 | -102/+215 |
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| * | | | Merge pull request #1709 from rqou/coolrunner2_counter | Claire Wolf | 2020-02-27 | 3 | -0/+165 |
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