| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-08 | 1 | -5/+9 |
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| | * | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 31 | -228/+236 |
| | |\ | | | | | | | Rename abc_* names/attributes to more precisely be abc9_* | ||||
| | | * | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 4 | -181/+9 |
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| | * | | | Add comment on why partial multipliers are 18x18 | Eddie Hung | 2019-10-04 | 1 | -4/+8 |
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| | * | | | Fix typo in check_label() | Eddie Hung | 2019-10-04 | 1 | -1/+1 |
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| * | | | Cleanup | Eddie Hung | 2019-10-07 | 1 | -7/+2 |
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| * | | | Rename $currQ to $abc9_currQ | Eddie Hung | 2019-10-07 | 1 | -46/+46 |
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| * | | | Update comments in abc9_map.v | Eddie Hung | 2019-10-07 | 1 | -131/+57 |
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| * | | | Remove -D_ABC9 | Eddie Hung | 2019-10-07 | 1 | -2/+0 |
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| * | | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 4 | -230/+200 |
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| * | | | abc -> abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+3 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-04 | 4 | -181/+9 |
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| | * | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -2/+6 |
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| | * | | Remove DSP48E1 from *_cells_xtra.v | Eddie Hung | 2019-10-04 | 3 | -178/+2 |
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| * | | | Use read_args for read_verilog | Eddie Hung | 2019-10-04 | 1 | -3/+6 |
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| * | | | Fix merge issues | Eddie Hung | 2019-10-04 | 2 | -9/+10 |
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| * | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 31 | -278/+294 |
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| | * | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 31 | -227/+235 |
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| | * | Panic over. Model was elsewhere. Re-arrange for consistency | Eddie Hung | 2019-10-04 | 5 | -31/+4 |
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| | * | Oops | Eddie Hung | 2019-10-04 | 1 | -1/+1 |
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| | * | Ohmilord this wasn't added all this time!?! | Eddie Hung | 2019-10-04 | 1 | -0/+29 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-03 | 6 | -2/+184 |
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| | * | ecp5: Fix shuffle_enable port | David Shah | 2019-10-01 | 1 | -2/+2 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | ecp5: Add support for mapping 36-bit wide PDP BRAMs | David Shah | 2019-10-01 | 6 | -1/+183 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | English | Eddie Hung | 2019-10-03 | 1 | -3/+3 |
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| * | | More fixes | Eddie Hung | 2019-10-01 | 1 | -16/+16 |
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| * | | Escape Verilog identifiers for legality outside of Yosys | Eddie Hung | 2019-10-01 | 1 | -48/+48 |
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| * | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 2 | -111/+118 |
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| * | | Add explanation to abc_map.v | Eddie Hung | 2019-09-30 | 1 | -0/+16 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 8 | -124/+122 |
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| | * | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 6 | -122/+46 |
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| | * | synth_xilinx: Support latches, remove used-up FF init values. | Marcin Kościelnicki | 2019-09-30 | 2 | -2/+76 |
| | | | | | | | | | Fixes #1387. | ||||
| * | | Missing endmodule | Eddie Hung | 2019-09-29 | 1 | -0/+1 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 19 | -31/+3401 |
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| | * | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 19 | -31/+3395 |
| | |\ | | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5) | ||||
| | | * | Re-order | Eddie Hung | 2019-09-27 | 2 | -2/+2 |
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| | | * | Missing (* mul2dsp *) for sliceB | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
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| | | * | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once | Eddie Hung | 2019-09-26 | 1 | -9/+4 |
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| | | * | Typo | Eddie Hung | 2019-09-26 | 1 | -1/+1 |
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| | | * | select once | Eddie Hung | 2019-09-26 | 2 | -8/+12 |
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| | | * | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 3 | -38/+14 |
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| | | * | mul2dsp.v slice names | Eddie Hung | 2019-09-25 | 1 | -5/+5 |
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| | | * | Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit | Eddie Hung | 2019-09-25 | 1 | -3/+1 |
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| | | * | Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" | Eddie Hung | 2019-09-25 | 1 | -2/+6 |
| | | | | | | | | | | | | | This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1. | ||||
| | | * | Revert "No need for $__mul anymore?" | Eddie Hung | 2019-09-25 | 1 | -8/+8 |
| | | | | | | | | | | | | | This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827. | ||||
| | | * | Only wreduce on t:$add | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
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| | | * | Remove _TECHMAP_CELLTYPE_ check since all $mul | Eddie Hung | 2019-09-25 | 1 | -6/+2 |
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| | | * | No need for $__mul anymore? | Eddie Hung | 2019-09-25 | 1 | -8/+8 |
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| | | * | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 1 | -0/+1 |
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| | | * | Oops. Actually use __NAME__ in ABC_DSP48E1 macro | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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