aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Expand)AuthorAgeFilesLines
* Remove clkpartEddie Hung2019-12-051-4/+0
* Revert "Special abc9_clock wire to contain only clock signal"Eddie Hung2019-12-051-10/+12
* Missing wire declarationEddie Hung2019-12-041-0/+1
* abc9_map.v to transform INIT=1 to INIT=0Eddie Hung2019-12-041-118/+201
* Oh deary meEddie Hung2019-12-041-4/+4
* output reg Q -> output Q to suppress warningEddie Hung2019-12-041-8/+8
* abc9_map.v to do `zinit' and make INIT = 1'b0Eddie Hung2019-12-041-70/+112
* Add abc9_init wire, attach to abc9_flop cellEddie Hung2019-12-031-2/+12
* Revert "Add INIT value to abc9_control"Eddie Hung2019-12-031-8/+8
* techmap abc_unmap.v before xilinx_srl -fixedEddie Hung2019-12-031-6/+5
* Add INIT value to abc9_controlEddie Hung2019-12-021-8/+8
* clkpart -unpart into 'finalize'Eddie Hung2019-11-281-3/+4
* ean call after abc{,9}Eddie Hung2019-11-271-1/+2
* Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dffEddie Hung2019-11-273-25/+30
|\
| * xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-263-25/+30
* | Move 'clean' from map_luts to finalizeEddie Hung2019-11-261-1/+1
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-253-5/+11
|\|
| * clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-1/+5
| * xilinx: Use INV instead of LUT1 when applicableMarcin Kościelnicki2019-11-251-2/+6
| * coolrunner2: remove spurious log_pop() call, fixes #1463Martin Pietryka2019-11-231-2/+0
* | Special abc9_clock wire to contain only clock signalEddie Hung2019-11-251-12/+10
* | For abc9, run clkpart before ff_map and after abc9Eddie Hung2019-11-231-0/+2
* | Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-221-0/+2
|\|
| * gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
* | Merge branch 'eddie/xaig_dff_adff' into xaig_dffEddie Hung2019-11-211-12/+16
|\ \
| * | Do not drop async control signals in abc_map.vEddie Hung2019-11-191-12/+16
* | | Add blackbox model for $__ABC9_FF_ so that clock partitioning worksEddie Hung2019-11-201-0/+3
* | | Fix INIT valuesEddie Hung2019-11-201-4/+4
|/ /
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-1941-23094/+31993
|\|
| * Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-198-43/+547
| |\
| | * Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
| | * add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
| | * Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-164-15/+439
| | |\
| | * | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-4/+4
| | * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1122-22988/+30572
| | |\ \
| | * | | fix wide lutsPepijn de Vos2019-11-061-12/+12
| | * | | add IOBUFPepijn de Vos2019-10-282-1/+10
| | * | | add tristate buffer and testPepijn de Vos2019-10-282-2/+8
| | * | | More formattingPepijn de Vos2019-10-281-55/+49
| | * | | really really fix formatting maybePepijn de Vos2019-10-281-41/+41
| | * | | undo formatting fuckupPepijn de Vos2019-10-281-25/+25
| | * | | add wide lutsPepijn de Vos2019-10-283-36/+119
| | * | | add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
| | * | | ALU sim tweaksPepijn de Vos2019-10-241-11/+11
| | * | | add a few more missing dffPepijn de Vos2019-10-211-7/+16
| | * | | add negedge DFFPepijn de Vos2019-10-212-15/+139
| | * | | use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
| | * | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-10-2158-1315/+24105
| | |\ \ \
| | * | | | remove duplicate DFFRPepijn de Vos2019-10-161-10/+0
| | * | | | Revert "add MUX support"Pepijn de Vos2019-09-063-17/+0
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-15 11:11:29 +0000