iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Towards Xilinx bram support	Clifford Wolf	2015-01-04	3	-13/+182
*	Progress in memory_bram	Clifford Wolf	2014-12-31	1	-3/+3
*	Added memory_bram (not functional yet)	Clifford Wolf	2014-12-31	1	-0/+20
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-1/+5
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15	1	-18/+18
*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24	1	-2/+2
*	Added "techmap -share_map" option	Clifford Wolf	2013-11-24	1	-4/+4
*	Fixed xilinx/example_sim_counter test bench	Clifford Wolf	2013-11-24	1	-1/+1
*	Added more generic _TECHMAP_ wire mechanism to techmap pass	Clifford Wolf	2013-11-23	1	-1/+1
*	[EXAMPLES] Ported the mojo counter example to Zynq ZED board.	James Walmsley	2013-10-27	4	-0/+56
*	Cleanups in xilinx examples	Clifford Wolf	2013-10-27	3	-144/+28
*	Added synth_xilinx command	Clifford Wolf	2013-10-27	2	-0/+219
*	Moved simple xilinx counter sim example to subdir	Clifford Wolf	2013-10-27	3	-0/+0
*	Xilinx mojo_counter example is now working	Clifford Wolf	2013-10-27	3	-4/+9
*	Renamed techlibs/xilinx7 to techlibs/xilinx	Clifford Wolf	2013-10-26	8	-0/+316