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* Merge branch 'master' into xc7dspDavid Shah2019-08-3010-218/+682
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| * Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendorEddie Hung2019-08-281-3/+8
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| * xilinx: Add SRLC16E primitive.Marcin Kościelnicki2019-08-271-1/+21
| | | | | | | | Fixes #1331.
| * Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-261-0/+8
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| | * Add undocumented featureEddie Hung2019-08-231-0/+8
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| * | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-1/+1
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| | * Forgot oneEddie Hung2019-08-231-1/+2
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| * | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-11/+22
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| | * Put abc_* attributes above portEddie Hung2019-08-231-7/+14
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| * | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-235-30/+39
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| | * Merge pull request #1209 from YosysHQ/eddie/synth_xilinxEddie Hung2019-08-204-16/+19
| | |\ | | | | | | | | [WIP] synth xilinx renaming, as per #1184
| | | * Merge remote-tracking branch 'origin/master' into eddie/synth_xilinxEddie Hung2019-08-203-6/+6
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| | | * | Update Makefile tooEddie Hung2019-07-181-2/+2
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| | | * | Work in progress for renaming labels/options in synth_xilinxEddie Hung2019-07-183-14/+17
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| | * | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-191-2/+2
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| | * | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modulesEddie Hung2019-08-161-8/+20
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| * | | move attributes to wiresMarcin Kościelnicki2019-08-136-283/+537
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| * | | minor review fixesMarcin Kościelnicki2019-08-131-1/+1
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| * | | review fixesMarcin Kościelnicki2019-08-131-18/+27
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| * | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-136-71/+220
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
* | | xilinx: Rework labels for faster Verilator testingDavid Shah2019-08-131-1/+5
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-121-1/+1
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| * | stoi -> atoiEddie Hung2019-08-071-1/+1
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* | | Pack partial-product adder DSP48E1 packingEddie Hung2019-08-091-0/+2
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* | | Remove signed from ports in +/xilinx/dsp_map.vEddie Hung2019-08-081-1/+1
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* | | Combine techmap callsEddie Hung2019-08-081-2/+1
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* | | Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
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* | | INMODE is 5 bitsEddie Hung2019-08-081-1/+1
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* | | Fix copy-pasta typoEddie Hung2019-08-081-2/+2
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* | | DSP48E1 sim model: add SIMD testsDavid Shah2019-08-083-3/+113
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | DSP48E1 model: test CE inputsDavid Shah2019-08-082-7/+17
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | DSP48E1 sim model: fix seq tests and add preadder testsDavid Shah2019-08-082-6/+91
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | DSP48E1 sim model: seq test workingDavid Shah2019-08-083-16/+60
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-082-8/+13
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | [wip] sim model testingDavid Shah2019-08-084-15/+77
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | [wip] sim model testingDavid Shah2019-08-083-40/+360
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-071-6/+82
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-8/+75
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
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* | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-012-5/+5
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| * | RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
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| * | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Add paramsEddie Hung2019-07-181-0/+6
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* | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
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* | Make all operands signedEddie Hung2019-07-171-1/+1
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* | Update commentEddie Hung2019-07-171-5/+3
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* | SignednessEddie Hung2019-07-162-8/+8
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* | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
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* | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-163-5/+9
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