iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add whitebox support to DRAM	Eddie Hung	2019-05-23	5	-24/+26
*	shift register inference before mux	Eddie Hung	2019-05-22	1	-3/+3
*	Fix/workaround symptom unveiled by #1023	Eddie Hung	2019-05-21	1	-4/+14
*	Instead of MUXCY/XORCY use CARRY4 (with timing)	Eddie Hung	2019-05-21	4	-11/+20
*	Modify LUT area cost to be same as old abc	Eddie Hung	2019-05-21	1	-10/+9
*	Merge remote-tracking branch 'origin/master' into xc7mux	Eddie Hung	2019-05-21	2	-8/+23
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\| *	Add "stat -tech xilinx"	Clifford Wolf	2019-05-11	1	-1/+1
\| *	Add "synth_xilinx -arch"	Clifford Wolf	2019-05-07	1	-1/+13
\| *	Rename cells_map.v to prevent clash with ff_map.v	Eddie Hung	2019-05-03	1	-6/+8
* \|	Trim off leading 1'bx in A	Eddie Hung	2019-05-02	1	-7/+20
* \|	Add don't care optimisation	Eddie Hung	2019-05-02	1	-0/+11
* \|	Use new peepopt from #969	Eddie Hung	2019-05-02	1	-10/+15
* \|	Revert to pre-muxcover approach	Eddie Hung	2019-05-02	2	-25/+82
* \|	Missing help_mode	Eddie Hung	2019-05-02	1	-1/+1
* \|	Fix -nocarry	Eddie Hung	2019-05-02	1	-3/+3
* \|	Merge remote-tracking branch 'origin/master' into xc7mux	Eddie Hung	2019-05-02	3	-176/+116
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\| *	Back to passing all xc7srl tests!	Eddie Hung	2019-05-01	1	-5/+4
\| *	Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine	Eddie Hung	2019-05-01	1	-165/+97
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\| \| *	Refactor synth_xilinx to auto-generate doc	Eddie Hung	2019-04-26	1	-153/+95
\| * \|	WIP	Eddie Hung	2019-04-28	1	-36/+22
\| * \|	Move neg-pol to pos-pol mapping from ff_map to cells_map.v	Eddie Hung	2019-04-28	2	-9/+12
\| * \|	Revert synth_xilinx 'fine' label more to how it used to be...	Eddie Hung	2019-04-26	1	-21/+40
* \| \|	Fix spacing	Eddie Hung	2019-04-26	1	-4/+4
* \| \|	Apparently, this reduces number of MUXCY/XORCY	Eddie Hung	2019-04-26	1	-10/+9
* \| \|	Try a different approach with 'muxcover'	Eddie Hung	2019-04-26	2	-88/+36
* \| \|	Merge remote-tracking branch 'origin/master' into xc7mux	Eddie Hung	2019-04-26	1	-1/+0
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\| * \|	Where did this check come from!?!	Eddie Hung	2019-04-26	1	-1/+0
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* \|	Remove split_shiftx call	Eddie Hung	2019-04-26	1	-4/+1
* \|	Missing newline	Eddie Hung	2019-04-26	1	-1/+1
* \|	Cleanup superseded	Eddie Hung	2019-04-25	1	-11/+1
* \|	bitblast_shiftx -> split_shiftx	Eddie Hung	2019-04-25	1	-2/+2
* \|	synth_xilinx to call bitblast_shiftx	Eddie Hung	2019-04-25	1	-1/+4
* \|	Add -nocarry option to synth_xilinx	Eddie Hung	2019-04-24	1	-5/+14
* \|	Tweak	Eddie Hung	2019-04-22	1	-1/+1
* \|	Fix for A_WIDTH == 2 but B_WIDTH==3	Eddie Hung	2019-04-22	1	-1/+1
* \|	Trim A_WIDTH by Y_WIDTH-1	Eddie Hung	2019-04-22	1	-1/+1
* \|	Add comment	Eddie Hung	2019-04-22	1	-0/+3
* \|	Fix for mux_case_* mappings	Eddie Hung	2019-04-22	1	-17/+9
* \|	Fix for non-pow2 width muxes	Eddie Hung	2019-04-22	1	-9/+18
* \|	Add synth_xilinx -nomux option	Eddie Hung	2019-04-22	2	-4/+18
* \|	Cleanup, call pmux2shiftx even without -nosrl	Eddie Hung	2019-04-22	6	-45/+30
* \|	Merge remote-tracking branch 'origin/xc7srl' into xc7mux	Eddie Hung	2019-04-22	6	-31/+216
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\| *	Update help message	Eddie Hung	2019-04-22	1	-1/+1
\| *	Move 'shregmap -tech xilinx' into map_cells	Eddie Hung	2019-04-22	1	-17/+20
\| *	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-04-22	1	-0/+2
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\| \| *	Re-added clean after techmap in synth_xilinx	Clifford Wolf	2019-04-22	1	-0/+2
\| * \|	Tidy up, fix for -nosrl	Eddie Hung	2019-04-21	2	-12/+16
\| * \|	Merge branch 'map_cells_before_map_luts' into xc7srl	Eddie Hung	2019-04-21	1	-2/+2
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\| \| *	Merge branch 'master' into map_cells_before_map_luts	Eddie Hung	2019-04-21	5	-56/+76
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\| * \| \|	Add comments	Eddie Hung	2019-04-21	1	-0/+7