| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | | | | | | | | | | | | Fix RAM64M model to have 6 bit address bus | Eddie Hung | 2019-12-12 | 1 | -4/+4 | |
| | * | | | | | | | | | | | | | Add memory rules for RAM16X1D, RAM32M, RAM64M | Eddie Hung | 2019-12-12 | 2 | -0/+168 | |
| * | | | | | | | | | | | | | | Add unconditional match blocks for force RAM | Eddie Hung | 2019-12-16 | 1 | -4/+36 | |
| * | | | | | | | | | | | | | | Update xc7/xcu bram rules | Eddie Hung | 2019-12-16 | 1 | -8/+4 | |
| * | | | | | | | | | | | | | | Removing fixed attribute value to !ramstyle rules | Diego H | 2019-12-15 | 1 | -4/+4 | |
| * | | | | | | | | | | | | | | Merging attribute rules into a single match block; Adding tests | Diego H | 2019-12-15 | 1 | -18/+12 | |
| * | | | | | | | | | | | | | | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific | Diego H | 2019-12-13 | 1 | -0/+19 | |
| * | | | | | | | | | | | | | | Merge pull request #1533 from dh73/bram_xilinx | Eddie Hung | 2019-12-13 | 1 | -6/+9 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / / / / / |/| | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. | Diego H | 2019-12-12 | 1 | -5/+5 | |
| | * | | | | | | | | | | | | | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 | Diego H | 2019-12-12 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | Merge https://github.com/YosysHQ/yosys into bram_xilinx | Diego H | 2019-12-12 | 5 | -633/+868 | |
| | |\| | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | Adjusting Vivado's BRAM min bits threshold for RAMB18E1 | Diego H | 2019-11-27 | 1 | -2/+5 | |
| | | |_|_|_|_|_|_|_|_|_|_|/ | |/| | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 | |
| | |/ / / / / / / / / / / |/| | | | | | | | | | | | ||||||
| * | | | | | | | | | | | | xilinx: Add tristate buffer mapping. (#1528) | Marcin Kościelnicki | 2019-12-04 | 2 | -9/+16 | |
| * | | | | | | | | | | | | xilinx: Add models for LUTRAM cells. (#1537) | Marcin Kościelnicki | 2019-12-04 | 3 | -624/+831 | |
| * | | | | | | | | | | | | xilinx: Add missing blackbox cell for BUFPLL. | Marcin Kościelnicki | 2019-11-29 | 2 | -0/+21 | |
| |/ / / / / / / / / / / | ||||||
| * | | | | | | | | | / | xilinx: Add simulation models for IOBUF and OBUFT. | Marcin Kościelnicki | 2019-11-26 | 3 | -25/+30 | |
| | |_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | ||||||
| * | | | | | | | | | | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -1/+5 | |
| * | | | | | | | | | | xilinx: Use INV instead of LUT1 when applicable | Marcin Kościelnicki | 2019-11-25 | 1 | -2/+6 | |
| | |_|_|_|_|_|_|_|/ |/| | | | | | | | | ||||||
| * | | | | | | | | | xilinx: Add simulation models for MULT18X18* and DSP48A*. | Marcin Kościelnicki | 2019-11-19 | 3 | -132/+516 | |
| * | | | | | | | | | synth_xilinx: Merge blackbox primitive libraries. | Marcin Kościelnicki | 2019-11-06 | 11 | -23234/+29820 | |
| * | | | | | | | | | xilinx: Add URAM288 mapping for xcup | David Shah | 2019-10-23 | 5 | -2/+92 | |
| * | | | | | | | | | xilinx: Add support for UltraScale[+] BRAM mapping | David Shah | 2019-10-23 | 7 | -416/+1062 | |
| * | | | | | | | | | xilinx: Support multiplier mapping for all families. | Marcin Kościelnicki | 2019-10-22 | 9 | -9/+269 | |
| * | | | | | | | | | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg | Clifford Wolf | 2019-10-22 | 1 | -0/+1 | |
| |\ \ \ \ \ \ \ \ \ | ||||||
| | * | | | | | | | | | Call memory_dff before DSP mapping to reserve registers (fixes #1447) | N. Engelhardt | 2019-10-17 | 1 | -0/+1 | |
| * | | | | | | | | | | Makefile: don't assume python is called `python3` | Sean Cross | 2019-10-19 | 1 | -1/+1 | |
| |/ / / / / / / / / | ||||||
| * | | | | | | | / | xilinx: Add simulation model for IBUFG. | Marcin Kościelnicki | 2019-10-10 | 5 | -33/+14 | |
| | |_|_|_|_|_|_|/ |/| | | | | | | | ||||||
| * | | | | | | | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 11 | -112/+121 | |
| |\ \ \ \ \ \ \ \ | ||||||
| | * \ \ \ \ \ \ \ | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 4 | -181/+9 | |
| | |\ \ \ \ \ \ \ \ | | |_|_|_|_|_|/ / | |/| | | | | | / | | | |_|_|_|_|/ | | |/| | | | | | ||||||
| | * | | | | | | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 11 | -111/+120 | |
| | | |_|_|_|_|/ | |/| | | | | | ||||||
| * | | | | | | | Add comment on why partial multipliers are 18x18 | Eddie Hung | 2019-10-04 | 1 | -4/+8 | |
| * | | | | | | | Fix typo in check_label() | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
| | |/ / / / / |/| | | | | | ||||||
| * | | | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -2/+6 | |
| * | | | | | | Remove DSP48E1 from *_cells_xtra.v | Eddie Hung | 2019-10-04 | 3 | -178/+2 | |
| |/ / / / / | ||||||
| * | | | | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 6 | -122/+46 | |
| * | | | | | synth_xilinx: Support latches, remove used-up FF init values. | Marcin Kościelnicki | 2019-09-30 | 2 | -2/+76 | |
| | |_|_|/ |/| | | | ||||||
| * | | | | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 11 | -21/+3000 | |
| |\ \ \ \ | |_|_|/ |/| | | | ||||||
| | * | | | Re-order | Eddie Hung | 2019-09-27 | 1 | -1/+1 | |
| | * | | | Typo | Eddie Hung | 2019-09-26 | 1 | -1/+1 | |
| | * | | | select once | Eddie Hung | 2019-09-26 | 1 | -3/+5 | |
| | * | | | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 1 | -1/+3 | |
| | * | | | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 1 | -0/+1 | |
| | * | | | Oops. Actually use __NAME__ in ABC_DSP48E1 macro | Eddie Hung | 2019-09-25 | 1 | -1/+1 | |
| | * | | | Add (* techmap_autopurge *) to abc_unmap.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 | |
| | * | | | Add techmap_autopurge to outputs in abc_map.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 | |
| | * | | | Revert "Add a xilinx_finalise pass" | Eddie Hung | 2019-09-23 | 3 | -87/+0 | |
| | * | | | Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" | Eddie Hung | 2019-09-23 | 1 | -38/+38 | |
| | * | | | Revert "Vivado does not like zero width port connections" | Eddie Hung | 2019-09-23 | 1 | -2/+2 | |
| | * | | | Vivado does not like zero width port connections | Eddie Hung | 2019-09-23 | 1 | -2/+2 | |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |