| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added map, par and bitgen to xlinx7 example | Clifford Wolf | 2013-10-16 | 1 | -2/+39 |
| * | Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos) | Clifford Wolf | 2013-08-27 | 1 | -2/+10 |
| * | Added simple xilinx7 technology mapping files | Clifford Wolf | 2013-08-22 | 1 | -0/+41 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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