| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 1 | -2/+4 |
| * | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 1 | -0/+2 |
| * | synth_xilinx: Initial Spartan 6 block RAM inference support. | Marcin Kościelnicki | 2019-07-11 | 1 | -0/+319 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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