| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xilinx: Add simulation model for DSP48 (Virtex 4). | Marcin Kościelnicki | 2020-01-29 | 3 | -0/+304 |
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| * | xilinx: Test our DSP48A/DSP48A1 simulation models. | Marcin Kościelnicki | 2019-12-23 | 4 | -4/+359 |
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| * | Add pattern detection support for DSP48E1 model, check against vendor | Eddie Hung | 2019-09-18 | 2 | -4/+59 |
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| * | DSP48E1 sim model: add SIMD tests | David Shah | 2019-08-08 | 2 | -2/+112 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | DSP48E1 model: test CE inputs | David Shah | 2019-08-08 | 1 | -2/+9 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | DSP48E1 sim model: fix seq tests and add preadder tests | David Shah | 2019-08-08 | 2 | -6/+91 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | DSP48E1 sim model: seq test working | David Shah | 2019-08-08 | 2 | -10/+47 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | DSP48E1 sim model: Comb, no pre-adder, mode working | David Shah | 2019-08-08 | 1 | -6/+10 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | [wip] sim model testing | David Shah | 2019-08-08 | 3 | -13/+75 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | [wip] sim model testing | David Shah | 2019-08-08 | 2 | -0/+311 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Improved xilinx "bram1" test | Clifford Wolf | 2015-04-09 | 1 | -1/+2 |
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| * | Added support for initialized xilinx brams | Clifford Wolf | 2015-04-06 | 5 | -19/+90 |
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| * | Added Xilinx test case for initialized brams | Clifford Wolf | 2015-04-06 | 4 | -0/+80 |
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| * | Various cleanups in xilinx techlib | Clifford Wolf | 2015-01-18 | 1 | -0/+2 |
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| * | Refactoring of memory_bram and xilinx brams | Clifford Wolf | 2015-01-18 | 1 | -3/+7 |
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| * | Cleanups in xilinx bram descriptions | Clifford Wolf | 2015-01-07 | 1 | -4/+4 |
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| * | Xilinx RAMB36/RAMB18 memory_bram support complete | Clifford Wolf | 2015-01-06 | 1 | -1/+1 |
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| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-06 | 1 | -10/+49 |
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| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-06 | 2 | -1/+3 |
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| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-06 | 1 | -11/+18 |
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| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-06 | 2 | -4/+8 |
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| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-05 | 4 | -0/+148 |
 |
index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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