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| author | David Shah <dave@ds0.me> | 2019-08-08 10:52:04 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-08 10:52:04 +0100 |
| commit | e7dbe7bb3de256f0ea89eb07647799b1e8d65bbe (patch) | |
| tree | 5eaed8ee3756d23180d74bb3166128010da5b64f /techlibs/xilinx/tests | |
| parent | f6605c7dc0b1bcbc091b8283a741e24be25478b1 (diff) | |
| download | yosys-e7dbe7bb3de256f0ea89eb07647799b1e8d65bbe.tar.gz yosys-e7dbe7bb3de256f0ea89eb07647799b1e8d65bbe.tar.bz2 yosys-e7dbe7bb3de256f0ea89eb07647799b1e8d65bbe.zip | |
DSP48E1 sim model: seq test working
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/xilinx/tests')
| -rw-r--r-- | techlibs/xilinx/tests/test_dsp_model.sh | 2 | ||||
| -rw-r--r-- | techlibs/xilinx/tests/test_dsp_model.v | 55 |
2 files changed, 47 insertions, 10 deletions
diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh index 5455294da..3c7cfac30 100644 --- a/techlibs/xilinx/tests/test_dsp_model.sh +++ b/techlibs/xilinx/tests/test_dsp_model.sh @@ -4,7 +4,7 @@ sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > if [ ! -f "test_dsp_model_ref.v" ]; then cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v fi -for tb in mult_noreg_nopreadd_nocasc +for tb in mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc do iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v vvp -N ./test_dsp_model diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v index 86ff7ab40..b5574911b 100644 --- a/techlibs/xilinx/tests/test_dsp_model.v +++ b/techlibs/xilinx/tests/test_dsp_model.v @@ -94,7 +94,7 @@ module testbench; if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0; if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0; if ((OPMODE[6:4] == 3'b010 || OPMODE[6:4] == 3'b110) && PREG != 1) config_valid = 0; - if ((OPMODE[6:4] == 3'b100) && (PREG != 1 || OPMODE[3:0] != 4'b1000)) config_valid = 0; + if ((OPMODE[6:4] == 3'b100) && (PREG != 1 || OPMODE[3:0] != 4'b1000 || ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11)) config_valid = 0; if ((CARRYINSEL == 3'b100 || CARRYINSEL == 3'b101 || CARRYINSEL == 3'b111) && (PREG != 1)) config_valid = 0; if (OPMODE[6:4] == 3'b111) config_valid = 0; if ((ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11) && OPMODE[3:2] != 2'b00 && OPMODE[3:2] != 2'b10) config_valid = 0; @@ -119,14 +119,16 @@ module testbench; {OPMODE, CARRYCASCIN, CARRYIN, MULTSIGNIN} = 0; {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = ~0; - #5; - CLK = 1'b1; - #10; - CLK = 1'b0; - #5; - CLK = 1'b1; - #10; - CLK = 1'b0; + repeat (10) begin + #10; + CLK = 1'b1; + #10; + CLK = 1'b0; + #10; + CLK = 1'b1; + #10; + CLK = 1'b0; + end {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = 0; repeat (300) begin @@ -358,4 +360,39 @@ module mult_noreg_nopreadd_nocasc; .IS_INMODE_INVERTED (5'b0), .IS_OPMODE_INVERTED (7'b0) ) testbench (); +endmodule + +module mult_allreg_nopreadd_nocasc; + testbench #( + .ACASCREG (1), + .ADREG (1), + .ALUMODEREG (1), + .AREG (2), + .AUTORESET_PATDET ("NO_RESET"), + .A_INPUT ("DIRECT"), + .BCASCREG (1), + .BREG (2), + .B_INPUT ("DIRECT"), + .CARRYINREG (1), + .CARRYINSELREG (1), + .CREG (1), + .DREG (1), + .INMODEREG (1), + .MREG (1), + .OPMODEREG (1), + .PREG (1), + .SEL_MASK ("MASK"), + .SEL_PATTERN ("PATTERN"), + .USE_DPORT ("FALSE"), + .USE_MULT ("DYNAMIC"), + .USE_PATTERN_DETECT ("NO_PATDET"), + .USE_SIMD ("ONE48"), + .MASK (48'h3FFFFFFFFFFF), + .PATTERN (48'h000000000000), + .IS_ALUMODE_INVERTED(4'b0), + .IS_CARRYIN_INVERTED(1'b0), + .IS_CLK_INVERTED (1'b0), + .IS_INMODE_INVERTED (5'b0), + .IS_OPMODE_INVERTED (7'b0) + ) testbench (); endmodule
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