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| * | | Addressed review commentsMiodrag Milanovic2019-12-211-2/+3
| * | | iopad no op for compatibility with old scriptsMiodrag Milanovic2019-12-211-0/+3
| * | | Make iopad option default for all xilinx flowsMiodrag Milanovic2019-12-211-14/+5
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| * | Revert "Optimise write_xaiger"Eddie Hung2019-12-201-5/+0
| * | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-191-0/+5
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| | * | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-061-0/+5
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* | | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-301-2/+14
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-191-4/+12
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| * | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-181-0/+1
| * | xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-181-4/+11
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-061-9/+8
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| * xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-041-9/+8
* | Remove clkpartEddie Hung2019-12-051-4/+0
* | techmap abc_unmap.v before xilinx_srl -fixedEddie Hung2019-12-031-6/+5
* | clkpart -unpart into 'finalize'Eddie Hung2019-11-281-3/+4
* | ean call after abc{,9}Eddie Hung2019-11-271-1/+2
* | Move 'clean' from map_luts to finalizeEddie Hung2019-11-261-1/+1
* | For abc9, run clkpart before ff_map and after abc9Eddie Hung2019-11-231-0/+2
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-191-30/+76
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| * synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-061-22/+3
| * xilinx: Add URAM288 mapping for xcupDavid Shah2019-10-231-1/+23
| * xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-231-1/+6
| * xilinx: Support multiplier mapping for all families.Marcin Kościelnicki2019-10-221-8/+45
| * Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-171-0/+1
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-081-5/+9
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| * Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-081-7/+8
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| | * Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-041-3/+7
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| * | | Add comment on why partial multipliers are 18x18Eddie Hung2019-10-041-4/+8
| * | | Fix typo in check_label()Eddie Hung2019-10-041-1/+1
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* | | Remove -D_ABC9Eddie Hung2019-10-071-2/+0
* | | abc -> abc9Eddie Hung2019-10-041-3/+3
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-041-3/+7
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| * | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-2/+6
* | | Use read_args for read_verilogEddie Hung2019-10-041-3/+6
* | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-041-6/+7
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| * | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-6/+7
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-291-4/+32
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| * Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-291-4/+32
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| | * Re-orderEddie Hung2019-09-271-1/+1
| | * TypoEddie Hung2019-09-261-1/+1
| | * select onceEddie Hung2019-09-261-3/+5
| | * Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-1/+3
| | * Call 'wreduce' after mul2dsp to avoid unextend()Eddie Hung2019-09-251-0/+1
| | * Revert "Add a xilinx_finalise pass"Eddie Hung2019-09-231-2/+0
| | * Add a xilinx_finalise passEddie Hung2019-09-231-0/+2
| | * Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-201-1/+1
| | * Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-191-1/+3
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| | * | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2Eddie Hung2019-09-191-1/+4
| | * | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-181-6/+15
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| | * | | Missing spaceEddie Hung2019-09-111-0/+1
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