| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q | Eddie Hung | 2019-12-16 | 1 | -4/+4 |
| * | Disable RAM16X1D match rule; carry-over from LUT4 arches | Eddie Hung | 2019-12-13 | 1 | -6/+9 |
| * | Add RAM32X6SDP and RAM64X3SDP modes | Eddie Hung | 2019-12-12 | 1 | -0/+40 |
| * | Add memory rules for RAM16X1D, RAM32M, RAM64M | Eddie Hung | 2019-12-12 | 1 | -0/+64 |
| * | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 1 | -0/+60 |
 |
index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
| aboutsummaryrefslogtreecommitdiffstats |