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* xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
* xilinx: gate specify/attributes from iverilogEddie Hung2020-05-141-1/+3
* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-141-1/+19
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-96/+126
* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-141-4/+0
* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-141-4/+4
* xilinx: consider DSP48E1.ADREGEddie Hung2020-03-041-3/+3
* xilinx: improve specify for DSP48E1Eddie Hung2020-03-041-32/+116
* xilinx: Update RAMB* specify entriesEddie Hung2020-02-271-11/+42
* xilinx: add delays to INVEddie Hung2020-02-271-0/+3
* Make +/xilinx/cells_sim.v legalEddie Hung2020-02-271-76/+78
* Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-271-80/+492
* Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happyEddie Hung2020-02-271-14/+12
* Fix tests by gating some specify constructs from iverilogEddie Hung2020-02-271-0/+16
* abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-271-2/+6
* Update xilinx for ABC9Eddie Hung2020-02-271-8/+15
* Fix commented out specify statementEddie Hung2020-02-271-6/+6
* xilinx: improve specify functionalityEddie Hung2020-02-271-420/+445
* xilinx: use specify blocks in place of abc9_{arrival,required}Eddie Hung2020-02-271-176/+404
* Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-271-3/+70
* abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-271-0/+83
* Merge pull request #1661 from YosysHQ/eddie/abc9_requiredEddie Hung2020-02-051-81/+314
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| * abc9_ops: generate flop box ids, add abc9_required to FD* cellsEddie Hung2020-01-141-12/+45
| * Add abc9_required to DSP48E1.{A,B,C,D,PCIN}Eddie Hung2020-01-101-38/+117
| * Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req...Eddie Hung2020-01-081-3/+80
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| * \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_r...Eddie Hung2020-01-061-59/+68
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| * | | Update some abc9_arrival times, add abc9_required timesEddie Hung2019-12-271-24/+164
* | | | xilinx: Add simulation model for DSP48 (Virtex 4).Marcin Kościelnicki2020-01-291-1/+229
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* | | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2020-01-061-51/+59
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| * \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-061-0/+77
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-21/+41
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| * | | | Re-arrange FD orderEddie Hung2019-12-311-77/+77
| * | | | FDCE ports to be alphabeticalEddie Hung2019-12-311-3/+3
| * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-301-3/+3
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
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| * \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-4/+197
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| * | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-191-8/+8
| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-191-12/+47
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| * \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-061-0/+797
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| * | | | | | | | Oh deary meEddie Hung2019-12-041-4/+4
| * | | | | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dffEddie Hung2019-11-271-0/+28
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| * \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-251-1/+5
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| * \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-191-0/+522
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| * | | | | | | | | | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-051-208/+16
| * | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-041-47/+47
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| * | | | | | | | | | | | More fixesEddie Hung2019-10-011-16/+16
| * | | | | | | | | | | | Escape Verilog identifiers for legality outside of YosysEddie Hung2019-10-011-48/+48
| * | | | | | | | | | | | Remove need for $currQ port connectionEddie Hung2019-09-301-80/+80
| * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-301-0/+44
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