iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix name clash	Eddie Hung	2019-06-13	1	-4/+8
*	Move neg-pol to pos-pol mapping from ff_map to cells_map.v	Eddie Hung	2019-06-12	1	-0/+8
*	Remove wide mux inference	Eddie Hung	2019-06-12	1	-120/+0
*	$__XILINX_MUX_ -> $__XILINX_SHIFTX	Eddie Hung	2019-06-06	1	-9/+9
*	Fix muxcover and its techmapping	Eddie Hung	2019-06-06	1	-2/+2
*	Run muxpack and muxcover in synth_xilinx	Eddie Hung	2019-06-06	1	-0/+12
*	Cleanup	Eddie Hung	2019-06-05	1	-10/+0
*	Fix name clash	Eddie Hung	2019-06-04	1	-11/+11
*	Add mux_map.v for wide mux	Eddie Hung	2019-06-04	1	-21/+14
*	Fix/workaround symptom unveiled by #1023	Eddie Hung	2019-05-21	1	-4/+14
*	Merge remote-tracking branch 'origin/master' into xc7mux	Eddie Hung	2019-05-21	1	-6/+8
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\| *	Rename cells_map.v to prevent clash with ff_map.v	Eddie Hung	2019-05-03	1	-6/+8
* \|	Trim off leading 1'bx in A	Eddie Hung	2019-05-02	1	-7/+20
* \|	Add don't care optimisation	Eddie Hung	2019-05-02	1	-0/+11
* \|	Revert to pre-muxcover approach	Eddie Hung	2019-05-02	1	-17/+77
* \|	Merge remote-tracking branch 'origin/master' into xc7mux	Eddie Hung	2019-05-02	1	-0/+8
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\| *	Move neg-pol to pos-pol mapping from ff_map to cells_map.v	Eddie Hung	2019-04-28	1	-0/+8
* \|	Fix spacing	Eddie Hung	2019-04-26	1	-4/+4
* \|	Try a different approach with 'muxcover'	Eddie Hung	2019-04-26	1	-67/+15
* \|	Cleanup superseded	Eddie Hung	2019-04-25	1	-11/+1
* \|	Tweak	Eddie Hung	2019-04-22	1	-1/+1
* \|	Fix for A_WIDTH == 2 but B_WIDTH==3	Eddie Hung	2019-04-22	1	-1/+1
* \|	Trim A_WIDTH by Y_WIDTH-1	Eddie Hung	2019-04-22	1	-1/+1
* \|	Add comment	Eddie Hung	2019-04-22	1	-0/+3
* \|	Fix for mux_case_* mappings	Eddie Hung	2019-04-22	1	-17/+9
* \|	Fix for non-pow2 width muxes	Eddie Hung	2019-04-22	1	-9/+18
* \|	Add synth_xilinx -nomux option	Eddie Hung	2019-04-22	1	-0/+2
* \|	Merge remote-tracking branch 'origin/xc7srl' into xc7mux	Eddie Hung	2019-04-22	1	-0/+125
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\| *	Call shregmap twice -- once for variable, another for fixed	Eddie Hung	2019-04-05	1	-0/+3
\| *	techmap inside map_cells stage	Eddie Hung	2019-04-05	1	-1/+0
\| *	Use soft-logic, not LUT3 instantiation	Eddie Hung	2019-04-04	1	-4/+2
\| *	Cleanup comments	Eddie Hung	2019-04-04	1	-5/+4
\| *	Fine tune cells_map.v	Eddie Hung	2019-03-20	1	-19/+15
\| *	Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length	Eddie Hung	2019-03-19	1	-53/+20
\| *	Add support for variable length Xilinx SRL > 128	Eddie Hung	2019-03-19	1	-11/+67
\| *	Fix spacing	Eddie Hung	2019-03-19	1	-1/+1
\| *	Fix INIT for variable length SRs that have been bumped up one	Eddie Hung	2019-03-19	1	-1/+1
\| *	Only accept <128 for variable length, only if $shiftx exclusive	Eddie Hung	2019-03-16	1	-5/+1
\| *	Cleanup synth_xilinx	Eddie Hung	2019-03-15	1	-1/+1
\| *	Working	Eddie Hung	2019-03-15	1	-40/+69
\| *	Reverse bits in INIT parameter for Xilinx, since MSB is shifted first	Eddie Hung	2019-03-14	1	-16/+32
\| *	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-14	1	-86/+18
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\| * \|	Fix cells_map for SRL	Eddie Hung	2019-03-14	1	-19/+17
\| * \|	Refactor $__SHREG__ in cells_map.v	Eddie Hung	2019-03-13	1	-32/+24
\| * \|	Fix SRL16/32 techmap off-by-one	Eddie Hung	2019-02-28	1	-18/+24
\| * \|	synth_xilinx to call shregmap with enable support	Eddie Hung	2019-02-28	1	-23/+28
\| * \|	synth_xilinx to use shregmap with -params too	Eddie Hung	2019-02-28	1	-21/+18
\| * \|	Add techmap rule for $__SHREG_DFF_P_ to SRL16/32	Eddie Hung	2019-02-28	1	-0/+71
* \| \|	Fix cells_map.v some more	Eddie Hung	2019-04-11	1	-7/+7
* \| \|	More fine tuning	Eddie Hung	2019-04-11	1	-2/+2