| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added more FF types to xilinx/cells.v | Clifford Wolf | 2015-01-16 | 1 | -25/+28 |
| * | Added Xilinx MUXF7 and MUXF8 support | Clifford Wolf | 2015-01-15 | 1 | -0/+28 |
| * | Renamed $lut ports to follow A-Y naming scheme | Clifford Wolf | 2014-08-15 | 1 | -18/+18 |
| * | Added more generic _TECHMAP_ wire mechanism to techmap pass | Clifford Wolf | 2013-11-23 | 1 | -1/+1 |
| * | Renamed techlibs/xilinx7 to techlibs/xilinx | Clifford Wolf | 2013-10-26 | 1 | -0/+53 |
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index : iCE40/yosys | |
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