| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-06 | 1 | -140/+15 |
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| | * | Rework abc9's DSP48E1 model | Eddie Hung | 2020-01-01 | 1 | -140/+15 |
| * | | Fix attributes on $__ABC9_ASYNC[01] whitebox | Eddie Hung | 2019-12-31 | 1 | -2/+2 |
| * | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t | Eddie Hung | 2019-12-19 | 1 | -3/+11 |
| * | | Add blackbox model for $__ABC9_FF_ so that clock partitioning works | Eddie Hung | 2019-11-20 | 1 | -0/+3 |
| * | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 1 | -4/+1 |
| * | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 1 | -0/+7 |
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| * | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -0/+190 |
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index : iCE40/yosys | |
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