iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Expand)	Author	Age	Files	Lines
*	intel: Map M9K BRAM only on families that have it	Dan Ravensloft	2019-07-23	2	-0/+0
*	Changes in GoWin synth commands and ALU primitive support	Diego H	2018-12-03	1	-8/+8
*	Clean whitespace and permissions in techlibs/intel	Larry Doolittle	2017-10-05	4	-39/+39
*	Tested and working altsyncarm without init files	dh73	2017-10-01	2	-57/+59
*	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ...	dh73	2017-10-01	4	-0/+560

/** * \file * * \brief Instance description for TC2 * * Copyright (c) 2018 Microchip Technology Inc. * * \asf_license_start * * \page License * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. * You may obtain a copy of the Licence at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * \asf_license_stop * */ #ifndef _SAML22_TC2_INSTANCE_ #define _SAML22_TC2_INSTANCE_ /* ========== Register definition for TC2 peripheral ========== */ #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) #define REG_TC2_CTRLA (0x42002800) /**< \brief (TC2) Control A */ #define REG_TC2_CTRLBCLR (0x42002804) /**< \brief (TC2) Control B Clear */ #define REG_TC2_CTRLBSET (0x42002805) /**< \brief (TC2) Control B Set */ #define REG_TC2_EVCTRL (0x42002806) /**< \brief (TC2) Event Control */ #define REG_TC2_INTENCLR (0x42002808) /**< \brief (TC2) Interrupt Enable Clear */ #define REG_TC2_INTENSET (0x42002809) /**< \brief (TC2) Interrupt Enable Set */ #define REG_TC2_INTFLAG (0x4200280A) /**< \brief (TC2) Interrupt Flag Status and Clear */ #define REG_TC2_STATUS (0x4200280B) /**< \brief (TC2) Status */ #define REG_TC2_WAVE (0x4200280C) /**< \brief (TC2) Waveform Generation Control */ #define REG_TC2_DRVCTRL (0x4200280D) /**< \brief (TC2) Control C */ #define REG_TC2_DBGCTRL (0x4200280F) /**< \brief (TC2) Debug Control */ #define REG_TC2_SYNCBUSY (0x42002810) /**< \brief (TC2) Synchronization Status */ #define REG_TC2_COUNT16_COUNT (0x42002814) /**< \brief (TC2) COUNT16 Count */ #define REG_TC2_COUNT16_CC0 (0x4200281C) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ #define REG_TC2_COUNT16_CC1 (0x4200281E) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ #define REG_TC2_COUNT16_CCBUF0 (0x42002830) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ #define REG_TC2_COUNT16_CCBUF1 (0x42002832) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ #define REG_TC2_COUNT32_COUNT (0x42002814) /**< \brief (TC2) COUNT32 Count */ #define REG_TC2_COUNT32_CC0 (0x4200281C) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ #define REG_TC2_COUNT32_CC1 (0x42002820) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ #define REG_TC2_COUNT32_CCBUF0 (0x42002830) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ #define REG_TC2_COUNT32_CCBUF1 (0x42002834) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ #define REG_TC2_COUNT8_COUNT (0x42002814) /**< \brief (TC2) COUNT8 Count */ #define REG_TC2_COUNT8_PER (0x4200281B) /**< \brief (TC2) COUNT8 Period */ #define REG_TC2_COUNT8_CC0 (0x4200281C) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ #define REG_TC2_COUNT8_CC1 (0x4200281D) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ #define REG_TC2_COUNT8_PERBUF (0x4200282F) /**< \brief (TC2) COUNT8 Period Buffer */ #define REG_TC2_COUNT8_CCBUF0 (0x42002830) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ #define REG_TC2_COUNT8_CCBUF1 (0x42002831) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ #else #define REG_TC2_CTRLA (*(RwReg *)0x42002800UL) /**< \brief (TC2) Control A */ #define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42002804UL) /**< \brief (TC2) Control B Clear */ #define REG_TC2_CTRLBSET (*(RwReg8 *)0x42002805UL) /**< \brief (TC2) Control B Set */ #define REG_TC2_EVCTRL (*(RwReg16*)0x42002806UL) /**< \brief (TC2) Event Control */ #define REG_TC2_INTENCLR (*(RwReg8 *)0x42002808UL) /**< \brief (TC2) Interrupt Enable Clear */ #define REG_TC2_INTENSET (*(RwReg8 *)0x42002809UL) /**< \brief (TC2) Interrupt Enable Set */ #define REG_TC2_INTFLAG (*(RwReg8 *)0x4200280AUL) /**< \brief (TC2) Interrupt Flag Status and Clear */ #define REG_TC2_STATUS (*(RwReg8 *)0x4200280BUL) /**< \brief (TC2) Status */ #define REG_TC2_WAVE (*(RwReg8 *)0x4200280CUL) /**< \brief (TC2) Waveform Generation Control */ #define REG_TC2_DRVCTRL (*(RwReg8 *)0x4200280DUL) /**< \brief (TC2) Control C */ #define REG_TC2_DBGCTRL (*(RwReg8 *)0x4200280FUL) /**< \brief (TC2) Debug Control */ #define REG_TC2_SYNCBUSY (*(RoReg *)0x42002810UL) /**< \brief (TC2) Synchronization Status */ #define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42002814UL) /**< \brief (TC2) COUNT16 Count */ #define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4200281CUL) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ #define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200281EUL) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ #define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x42002830UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ #define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x42002832UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ #define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42002814UL) /**< \brief (TC2) COUNT32 Count */ #define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4200281CUL) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ #define REG_TC2_COUNT32_CC1 (*(RwReg *)0x42002820UL) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ #define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x42002830UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ #define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x42002834UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ #define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42002814UL) /**< \brief (TC2) COUNT8 Count */ #define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4200281BUL) /**< \brief (TC2) COUNT8 Period */ #define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4200281CUL) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ #define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4200281DUL) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ #define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4200282FUL) /**< \brief (TC2) COUNT8 Period Buffer */ #define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x42002830UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ #define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x42002831UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for TC2 peripheral ========== */ #define TC2_CC_NUM 2 #define TC2_DMAC_ID_MC_0 26 #define TC2_DMAC_ID_MC_1 27 #define TC2_DMAC_ID_MC_LSB 26 #define TC2_DMAC_ID_MC_MSB 27 #define TC2_DMAC_ID_MC_SIZE 2 #define TC2_DMAC_ID_OVF 25 // Indexes of DMA Overflow trigger #define TC2_EXT 0 #define TC2_GCLK_ID 24 #define TC2_MASTER 1 #define TC2_OW_NUM 2 #endif /* _SAML22_TC2_INSTANCE_ */