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* Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-031-0/+2
|\ | | | | Improve pmgen, Add "peepopt" pass with shift-mul pattern
| * Run "peepopt" in generic "synth" pass and "synth_ice40"Clifford Wolf2019-04-301-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Cleanup ice40Eddie Hung2019-04-261-4/+6
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* ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware ↵Luke Wren2019-04-211-10/+19
| | | | experiments
* Remove ice40/cells_sim.v hack to avoid warning for blocking memory writesClifford Wolf2019-03-121-19/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typo in ice40_braminit help msgClifford Wolf2019-03-091-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #859 from smunaut/ice40_braminitClifford Wolf2019-03-094-37/+212
|\ | | | | iCE40 BRAM primitives init from file
| * ice40: Run ice40_braminit pass by defaultSylvain Munaut2019-03-081-0/+1
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * ice40: Add ice40_braminit pass to allow initialization of BRAM from fileSylvain Munaut2019-03-083-37/+211
| | | | | | | | | | | | | | | | This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will initialize content from a hex file. Same behavior is imlemented in the simulation model and in a new pass for actual synthesis Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: use 2 bits for READ/WRITE MODE for SB_RAM mapElms2019-02-281-2/+2
|/ | | | | | EBLIF output .param will only use necessary 2 bits Signed-off-by: Elms <elms@freshred.net>
* Merge pull request #740 from daveshah1/improve_dressClifford Wolf2019-02-221-1/+1
|\ | | | | Improve ABC netname preservation
| * ice40: Use abc -dress in synth_ice40David Shah2019-02-061-1/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Bugfix in ice40_dspClifford Wolf2019-02-212-20/+33
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add ice40 test_dsp_map test case generatorClifford Wolf2019-02-202-0/+99
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "synth_ice40 -dsp"Clifford Wolf2019-02-201-3/+27
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve iCE40 SB_MAC16 modelClifford Wolf2019-02-205-121/+179
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add first draft of functional SB_MAC16 modelClifford Wolf2019-02-194-53/+467
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-021-1/+1
|\ | | | | synth: add k-LUT mode
| * synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
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* | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
|/ | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Rename "fine:" label to "map:" in "synth_ice40"Clifford Wolf2018-12-161-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-161-0/+2
|\ | | | | equiv_opt: new command, for verifying optimization passes
| * equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-071-0/+2
| | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models.
* | Merge pull request #730 from smunaut/ffssr_dont_touchClifford Wolf2018-12-161-0/+3
|\ \ | | | | | | ice40: Honor the "dont_touch" attribute in FFSSR pass
| * | ice40: Honor the "dont_touch" attribute in FFSSR passSylvain Munaut2018-12-081-0/+3
| |/ | | | | | | | | | | | | This is useful if you want to place FF manually ... can't merge SR in those because it might make the manual placement invalid Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #725 from olofk/ram4k-initClifford Wolf2018-12-161-0/+19
|\ \ | | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosys
| * | Only use non-blocking assignments of SB_RAM40_4K for yosysOlof Kindgren2018-12-061-0/+19
| |/ | | | | | | | | | | | | | | | | | | | | In an initial statement, blocking assignments are normally used and e.g. verilator throws a warning if non-blocking ones are used. Yosys cannot however properly resolve the interdependencies if blocking assignments are used in the initialization of SB_RAM_40_4K and thus this has been used. This patch will change to use non-blocking assignments only for yosys
* / synth_ice40: split `map_gates` off `fine`.whitequark2018-12-061-0/+4
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* synth_ice40: add -noabc option, to use built-in LUT techmapping.whitequark2018-12-051-2/+16
| | | | This should be combined with -relut to get sensible results.
* opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-2/+2
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* synth_ice40: add -relut option, to run ice40_unlut and opt_lut.whitequark2018-12-051-1/+13
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* Extract ice40_unlut pass from ice40_opt.whitequark2018-12-053-13/+109
| | | | | | | | Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert them back to logic immediately. This is not desirable if the goal is to operate on $lut cells. If this is desirable, the same result as `ice40_opt -unlut` can be achieved by running simplemap and opt after ice40_unlut.
* ice40: Add option to only use CE if it'd be use by more than X FFsSylvain Munaut2018-11-271-0/+14
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Add iCE40 SB_SPRAM256KA simulation modelClifford Wolf2018-09-101-9/+30
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-204-10/+10
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LCDavid Shah2018-07-131-2/+6
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add "synth_ice40 -json"Clifford Wolf2018-06-131-9/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix ice40_opt for cases where a port is connected to a signal with width != 1Clifford Wolf2018-06-111-9/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Avoid mixing module port declaration styles in ice40 cells_sim.vOlof Kindgren2018-05-171-43/+23
| | | | | | The current code requires workarounds for several simulators For modelsim, the file must be compiled with -mixedansiports and xsim needs --relax.
* Improving vpr output support.Tim 'mithro' Ansell2018-04-182-4/+4
| | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`.
* synth_ice40: Rework the vpr blif output slightly.Tim 'mithro' Ansell2018-04-181-4/+8
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* Add "synth_ice40 -nodffe"Clifford Wolf2018-04-161-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Squelch trailing whitespace, including meta-whitespaceLarry Doolittle2018-03-111-3/+3
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* Fix port names in SB_IO_ODGraham Edgecombe2017-12-101-18/+18
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* Remove trailing comma from SB_IO_OD port listGraham Edgecombe2017-12-101-1/+1
| | | | This isn't compatible with Icarus Verilog.
* Fix spelling in -vpr help for synth_ice40Tim Ansell2017-12-081-1/+1
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* Add remaining UltraPlus cells to ice40 techlibDavid Shah2017-11-281-0/+263
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* Remove unnecessary keep attributesDavid Shah2017-11-181-5/+5
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* Merge branch 'master' into up5kDavid Shah2017-11-172-5/+29
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| * Add "synth_ice40 -vpr"Clifford Wolf2017-11-162-5/+29
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