| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge pull request #969 from YosysHQ/clifford/pmgenstuff | Clifford Wolf | 2019-05-03 | 1 | -0/+2 |
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| | * | Run "peepopt" in generic "synth" pass and "synth_ice40" | Clifford Wolf | 2019-04-30 | 1 | -0/+2 |
| * | | Cleanup ice40 | Eddie Hung | 2019-04-26 | 1 | -4/+6 |
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| * | ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware exp... | Luke Wren | 2019-04-21 | 1 | -10/+19 |
| * | Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes | Clifford Wolf | 2019-03-12 | 1 | -19/+0 |
| * | Fix typo in ice40_braminit help msg | Clifford Wolf | 2019-03-09 | 1 | -1/+1 |
| * | Merge pull request #859 from smunaut/ice40_braminit | Clifford Wolf | 2019-03-09 | 4 | -37/+212 |
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| | * | ice40: Run ice40_braminit pass by default | Sylvain Munaut | 2019-03-08 | 1 | -0/+1 |
| | * | ice40: Add ice40_braminit pass to allow initialization of BRAM from file | Sylvain Munaut | 2019-03-08 | 3 | -37/+211 |
| * | | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map | Elms | 2019-02-28 | 1 | -2/+2 |
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| * | Merge pull request #740 from daveshah1/improve_dress | Clifford Wolf | 2019-02-22 | 1 | -1/+1 |
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| | * | ice40: Use abc -dress in synth_ice40 | David Shah | 2019-02-06 | 1 | -1/+1 |
| * | | Bugfix in ice40_dsp | Clifford Wolf | 2019-02-21 | 2 | -20/+33 |
| * | | Add ice40 test_dsp_map test case generator | Clifford Wolf | 2019-02-20 | 2 | -0/+99 |
| * | | Add "synth_ice40 -dsp" | Clifford Wolf | 2019-02-20 | 1 | -3/+27 |
| * | | Improve iCE40 SB_MAC16 model | Clifford Wolf | 2019-02-20 | 5 | -121/+179 |
| * | | Add first draft of functional SB_MAC16 model | Clifford Wolf | 2019-02-19 | 4 | -53/+467 |
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| * | Merge pull request #772 from whitequark/synth_lut | Clifford Wolf | 2019-01-02 | 1 | -1/+1 |
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| | * | synth_ice40: use 4-LUT coarse synthesis mode. | whitequark | 2019-01-02 | 1 | -1/+1 |
| * | | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -1/+1 |
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| * | Rename "fine:" label to "map:" in "synth_ice40" | Clifford Wolf | 2018-12-16 | 1 | -1/+1 |
| * | Merge pull request #724 from whitequark/equiv_opt | Clifford Wolf | 2018-12-16 | 1 | -0/+2 |
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| | * | equiv_opt: pass -D EQUIV when techmapping. | whitequark | 2018-12-07 | 1 | -0/+2 |
| * | | Merge pull request #730 from smunaut/ffssr_dont_touch | Clifford Wolf | 2018-12-16 | 1 | -0/+3 |
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| | * | | ice40: Honor the "dont_touch" attribute in FFSSR pass | Sylvain Munaut | 2018-12-08 | 1 | -0/+3 |
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| * | | Merge pull request #725 from olofk/ram4k-init | Clifford Wolf | 2018-12-16 | 1 | -0/+19 |
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| | * | | Only use non-blocking assignments of SB_RAM40_4K for yosys | Olof Kindgren | 2018-12-06 | 1 | -0/+19 |
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| * / | synth_ice40: split `map_gates` off `fine`. | whitequark | 2018-12-06 | 1 | -0/+4 |
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| * | synth_ice40: add -noabc option, to use built-in LUT techmapping. | whitequark | 2018-12-05 | 1 | -2/+16 |
| * | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. | whitequark | 2018-12-05 | 1 | -2/+2 |
| * | synth_ice40: add -relut option, to run ice40_unlut and opt_lut. | whitequark | 2018-12-05 | 1 | -1/+13 |
| * | Extract ice40_unlut pass from ice40_opt. | whitequark | 2018-12-05 | 3 | -13/+109 |
| * | ice40: Add option to only use CE if it'd be use by more than X FFs | Sylvain Munaut | 2018-11-27 | 1 | -0/+14 |
| * | Add iCE40 SB_SPRAM256KA simulation model | Clifford Wolf | 2018-09-10 | 1 | -9/+30 |
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 4 | -10/+10 |
| * | ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC | David Shah | 2018-07-13 | 1 | -2/+6 |
| * | Add "synth_ice40 -json" | Clifford Wolf | 2018-06-13 | 1 | -9/+22 |
| * | Fix ice40_opt for cases where a port is connected to a signal with width != 1 | Clifford Wolf | 2018-06-11 | 1 | -9/+25 |
| * | Avoid mixing module port declaration styles in ice40 cells_sim.v | Olof Kindgren | 2018-05-17 | 1 | -43/+23 |
| * | Improving vpr output support. | Tim 'mithro' Ansell | 2018-04-18 | 2 | -4/+4 |
| * | synth_ice40: Rework the vpr blif output slightly. | Tim 'mithro' Ansell | 2018-04-18 | 1 | -4/+8 |
| * | Add "synth_ice40 -nodffe" | Clifford Wolf | 2018-04-16 | 1 | -2/+11 |
| * | Squelch trailing whitespace, including meta-whitespace | Larry Doolittle | 2018-03-11 | 1 | -3/+3 |
| * | Fix port names in SB_IO_OD | Graham Edgecombe | 2017-12-10 | 1 | -18/+18 |
| * | Remove trailing comma from SB_IO_OD port list | Graham Edgecombe | 2017-12-10 | 1 | -1/+1 |
| * | Fix spelling in -vpr help for synth_ice40 | Tim Ansell | 2017-12-08 | 1 | -1/+1 |
| * | Add remaining UltraPlus cells to ice40 techlib | David Shah | 2017-11-28 | 1 | -0/+263 |
| * | Remove unnecessary keep attributes | David Shah | 2017-11-18 | 1 | -5/+5 |
| * | Merge branch 'master' into up5k | David Shah | 2017-11-17 | 2 | -5/+29 |
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| | * | Add "synth_ice40 -vpr" | Clifford Wolf | 2017-11-16 | 2 | -5/+29 |
