| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Remove WIP ABC9 flop support | Eddie Hung | 2019-06-14 | 1 | -25/+25 |
| | | |||||
| * | Remove abc_flop{,_d} attributes from ice40/cells_sim.v | Eddie Hung | 2019-06-12 | 1 | -40/+20 |
| | | |||||
| * | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-10 | 1 | -0/+24 |
| |\ | |||||
| | * | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k | Simon Schubert | 2019-06-10 | 1 | -0/+24 |
| | | | |||||
| * | | Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now) | Eddie Hung | 2019-06-03 | 1 | -3/+3 |
| | | | |||||
| * | | Consistent with xilinx | Eddie Hung | 2019-06-03 | 1 | -1/+1 |
| | | | |||||
| * | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-05-31 | 1 | -1/+1 |
| |\ \ | |||||
| | * | | Use nonblocking | Eddie Hung | 2019-04-23 | 1 | -1/+1 |
| | | | | |||||
| * | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-21 | 1 | -0/+11 |
| |\ \ \ | |/ / |/| / | |/ | |||||
| | * | ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC | Sylvain Munaut | 2019-05-13 | 1 | -0/+11 |
| | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 1 | -10/+19 |
| |\| | |||||
| | * | ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware ↵ | Luke Wren | 2019-04-21 | 1 | -10/+19 |
| | | | | | | | | | experiments | ||||
| * | | Convert to use #945 | Eddie Hung | 2019-04-21 | 1 | -8/+2 |
| | | | |||||
| * | | ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set | Eddie Hung | 2019-04-19 | 1 | -3/+6 |
| | | | |||||
| * | | Fix SB_DFF comb model | Eddie Hung | 2019-04-18 | 1 | -1/+1 |
| | | | |||||
| * | | Missing close bracket | Eddie Hung | 2019-04-18 | 1 | -1/+1 |
| | | | |||||
| * | | Annotate SB_DFF* with abc_flop and abc_box_id | Eddie Hung | 2019-04-18 | 1 | -22/+49 |
| | | | |||||
| * | | Use new -wb flag for ABC flow | Eddie Hung | 2019-04-18 | 1 | -0/+2 |
| | | | |||||
| * | | Missing abc_flop_q attribute on SPRAM | Eddie Hung | 2019-04-17 | 1 | -1/+1 |
| | | | |||||
| * | | Mark seq output ports with "abc_flop_q" attr | Eddie Hung | 2019-04-17 | 1 | -24/+24 |
| | | | |||||
| * | | Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" | Eddie Hung | 2019-04-17 | 1 | -22/+0 |
| | | | | | | | | | This reverts commit a7632ab3326c5247b8152a53808413b259c13253. | ||||
| * | | Try using an ICE40_CARRY_LUT primitive to avoid ABC issues | Eddie Hung | 2019-04-17 | 1 | -0/+22 |
| | | | |||||
| * | | Add ice40 box files | Eddie Hung | 2019-04-16 | 1 | -0/+1 |
| |/ | |||||
| * | Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes | Clifford Wolf | 2019-03-12 | 1 | -19/+0 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | ice40: Add ice40_braminit pass to allow initialization of BRAM from file | Sylvain Munaut | 2019-03-08 | 1 | -37/+51 |
| | | | | | | | | | This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will initialize content from a hex file. Same behavior is imlemented in the simulation model and in a new pass for actual synthesis Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | Improve iCE40 SB_MAC16 model | Clifford Wolf | 2019-02-20 | 1 | -17/+10 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add first draft of functional SB_MAC16 model | Clifford Wolf | 2019-02-19 | 1 | -53/+175 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge pull request #724 from whitequark/equiv_opt | Clifford Wolf | 2018-12-16 | 1 | -0/+2 |
| |\ | | | | | equiv_opt: new command, for verifying optimization passes | ||||
| | * | equiv_opt: pass -D EQUIV when techmapping. | whitequark | 2018-12-07 | 1 | -0/+2 |
| | | | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models. | ||||
| * | | Only use non-blocking assignments of SB_RAM40_4K for yosys | Olof Kindgren | 2018-12-06 | 1 | -0/+19 |
| |/ | | | | | | | | | | | In an initial statement, blocking assignments are normally used and e.g. verilator throws a warning if non-blocking ones are used. Yosys cannot however properly resolve the interdependencies if blocking assignments are used in the initialization of SB_RAM_40_4K and thus this has been used. This patch will change to use non-blocking assignments only for yosys | ||||
| * | Add iCE40 SB_SPRAM256KA simulation model | Clifford Wolf | 2018-09-10 | 1 | -9/+30 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC | David Shah | 2018-07-13 | 1 | -2/+6 |
| | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | Avoid mixing module port declaration styles in ice40 cells_sim.v | Olof Kindgren | 2018-05-17 | 1 | -43/+23 |
| | | | | | | | The current code requires workarounds for several simulators For modelsim, the file must be compiled with -mixedansiports and xsim needs --relax. | ||||
| * | Squelch trailing whitespace, including meta-whitespace | Larry Doolittle | 2018-03-11 | 1 | -3/+3 |
| | | |||||
| * | Fix port names in SB_IO_OD | Graham Edgecombe | 2017-12-10 | 1 | -18/+18 |
| | | |||||
| * | Remove trailing comma from SB_IO_OD port list | Graham Edgecombe | 2017-12-10 | 1 | -1/+1 |
| | | | | | This isn't compatible with Icarus Verilog. | ||||
| * | Add remaining UltraPlus cells to ice40 techlib | David Shah | 2017-11-28 | 1 | -0/+263 |
| | | |||||
| * | Remove unnecessary keep attributes | David Shah | 2017-11-18 | 1 | -5/+5 |
| | | |||||
| * | Add some UltraPlus cells to ice40 techlib | David Shah | 2017-11-16 | 1 | -0/+103 |
| | | |||||
| * | Work around DDR dout sim glitches in ice40 SB_IO sim model | Clifford Wolf | 2016-02-07 | 1 | -1/+7 |
| | | |||||
| * | Merge pull request #108 from cseed/master | Clifford Wolf | 2015-12-07 | 1 | -1/+3 |
| |\ | | | | | Added LO to ICESTORM_LC for LUT cascade route. | ||||
| | * | Added LO to ICESTORM_LC for LUT cascade route. | Cotton Seed | 2015-12-06 | 1 | -1/+3 |
| | | | |||||
| * | | Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling | Clifford Wolf | 2015-11-06 | 1 | -2/+2 |
| | | | |||||
| * | | Fixed ice40 handling of negclk RAM40 | Clifford Wolf | 2015-09-10 | 1 | -8/+8 |
| |/ | |||||
| * | Improved handling of "keep" attributes in hierarchical designs in opt_clean | Clifford Wolf | 2015-08-12 | 1 | -2/+1 |
| | | |||||
| * | Added iCE40 WARMBOOT cell | Marcus Comstedt | 2015-08-06 | 1 | -0/+10 |
| | | |||||
| * | Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle) | Clifford Wolf | 2015-07-27 | 1 | -1/+0 |
| | | |||||
| * | iCE40 DFF sim models: init Q regs to 0 | Clifford Wolf | 2015-07-20 | 1 | -20/+43 |
| | | |||||
| * | Avoid tristate warning for blackbox ice40/cells_sim.v | Clifford Wolf | 2015-07-18 | 1 | -0/+2 |
| | | |||||
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
| | | |||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |