| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | better handling of lut and begin/end add | Miodrag Milanovic | 2019-09-18 | 1 | -4/+10 |
| * | Added simulation models for Efinix and Anlogic | Miodrag Milanovic | 2019-09-15 | 1 | -2/+62 |
| * | Added bram support | Miodrag Milanovic | 2019-08-04 | 1 | -1/+64 |
| * | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 1 | -1/+9 |
| * | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 1 | -0/+36 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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