| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Added $tribuf and $_TBUF_ cell types | Clifford Wolf | 2015-08-16 | 1 | -1/+1 | |
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| * | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 3 | -4/+4 | |
| | | | | | Smaller this time | |||||
| * | Adjust makefiles to work with out-of-tree builds | Clifford Wolf | 2015-08-12 | 2 | -12/+0 | |
| | | | | | This is based on work done by Larry Doolittle | |||||
| * | Added WORDS parameter to $meminit | Clifford Wolf | 2015-07-31 | 1 | -1/+2 | |
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| * | Added "synth -nofsm" | Clifford Wolf | 2015-07-02 | 1 | -1/+10 | |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 4 | -10/+10 | |
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| * | Added "synth -nordff -noalumacc" | Clifford Wolf | 2015-06-15 | 1 | -3/+20 | |
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| * | Added simplemap $lut support | Clifford Wolf | 2015-04-27 | 1 | -8/+2 | |
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| * | make all vector-size related integer params in $mem sim model signed | Clifford Wolf | 2015-04-05 | 1 | -6/+6 | |
| | | | | | | | this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory. | |||||
| * | Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types | Clifford Wolf | 2015-04-05 | 1 | -0/+29 | |
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| * | Added $assume cell type | Clifford Wolf | 2015-02-26 | 1 | -1/+18 | |
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| * | Added "stat" to "synth" and "synth_xilinx" | Clifford Wolf | 2015-02-15 | 1 | -0/+2 | |
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| * | Added final checks to "synth" and "synth_xilinx" | Clifford Wolf | 2015-02-15 | 1 | -7/+14 | |
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| * | Smaller default parameters in $mem simlib model | Clifford Wolf | 2015-02-15 | 1 | -2/+2 | |
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| * | Added $meminit support to "memory" command | Clifford Wolf | 2015-02-14 | 1 | -3/+15 | |
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| * | Added $meminit cell type | Clifford Wolf | 2015-02-14 | 1 | -0/+22 | |
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| * | Added "check" command | Clifford Wolf | 2015-02-13 | 1 | -0/+4 | |
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| * | Some test related fixes | Clifford Wolf | 2015-02-12 | 1 | -4/+4 | |
| | | | | | (incl. removal of three bad test cases) | |||||
| * | Added "make mklibyosys", some minor API changes | Clifford Wolf | 2015-02-01 | 1 | -1/+9 | |
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| * | Added "fsm -encfile" | Clifford Wolf | 2015-01-30 | 1 | -2/+9 | |
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| * | Added $equiv cell type | Clifford Wolf | 2015-01-19 | 1 | -1/+23 | |
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| * | Added cells.lib | Clifford Wolf | 2015-01-16 | 2 | -0/+109 | |
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| * | Added add_share_file Makefile macro | Clifford Wolf | 2015-01-08 | 1 | -25/+6 | |
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| * | Progress in memory_bram | Clifford Wolf | 2015-01-03 | 1 | -0/+3 | |
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| * | Added proper clkpol support to memory_bram | Clifford Wolf | 2015-01-02 | 1 | -1/+1 | |
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| * | New $mem simlib model | Clifford Wolf | 2015-01-02 | 1 | -95/+36 | |
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| * | Fixed simlib entries for $memrd and $memwr | Clifford Wolf | 2014-12-30 | 1 | -0/+2 | |
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| * | Fixed build with SMALL=1 | Clifford Wolf | 2014-12-30 | 1 | -0/+2 | |
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| * | Improvements in simplemap api, added $ne $nex $eq $eqx support | Clifford Wolf | 2014-12-24 | 1 | -49/+5 | |
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| * | Removed UTF-8 chars from techmap.v | Clifford Wolf | 2014-12-12 | 1 | -1/+1 | |
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| * | Added $dffe cell type | Clifford Wolf | 2014-12-08 | 2 | -1/+20 | |
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| * | Added $_DFFE_??_ cell types | Clifford Wolf | 2014-12-08 | 1 | -0/+32 | |
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| * | Added "abc" label in synth script | Clifford Wolf | 2014-10-31 | 1 | -6/+12 | |
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| * | Added "opt -full" alias for all more aggressive optimizations | Clifford Wolf | 2014-10-31 | 1 | -2/+6 | |
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| * | Added $_BUF_ cell type | Clifford Wolf | 2014-10-03 | 1 | -0/+6 | |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -1/+5 | |
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| * | Improvements in "synth" script | Clifford Wolf | 2014-09-18 | 1 | -8/+12 | |
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| * | Fixed $macc simlib model for zero-config | Clifford Wolf | 2014-09-16 | 1 | -1/+1 | |
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| * | Added "synth" command | Clifford Wolf | 2014-09-14 | 2 | -0/+154 | |
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| * | Using alumacc in techmap.v | Clifford Wolf | 2014-09-14 | 1 | -237/+33 | |
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| * | Fixed simlib $macc model for xilinx xsim | Clifford Wolf | 2014-09-08 | 1 | -1/+15 | |
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| * | Simplified $fa undef model | Clifford Wolf | 2014-09-08 | 1 | -1/+1 | |
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| * | Fixes and cleanups for blackbox.v | Clifford Wolf | 2014-09-08 | 2 | -70/+73 | |
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| * | Added $lcu cell type | Clifford Wolf | 2014-09-08 | 2 | -74/+31 | |
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| * | Added "$fa" cell type | Clifford Wolf | 2014-09-08 | 2 | -0/+28 | |
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| * | Using maccmap for $macc and $mul techmap | Clifford Wolf | 2014-09-07 | 1 | -190/+16 | |
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| * | Various bug fixes (related to $macc model testing) | Clifford Wolf | 2014-09-06 | 2 | -2/+2 | |
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| * | Added $macc SAT model | Clifford Wolf | 2014-09-06 | 2 | -6/+6 | |
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| * | Added $macc simlib model (also use as techmap rule for now) | Clifford Wolf | 2014-09-06 | 2 | -0/+172 | |
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| * | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 | 2 | -34/+5 | |
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index : iCE40/yosys | |
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