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| author | Clifford Wolf <clifford@clifford.at> | 2014-10-31 03:46:27 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-10-31 03:46:27 +0100 |
| commit | 74ef92b9c888fd05f03b4f679ecda6b04249e498 (patch) | |
| tree | bdb8fc71920a376fc91897d9dd5d663120c7d69f /techlibs/common | |
| parent | ab28491f271e3b02ba58dabb4b7033bcf17b6c25 (diff) | |
| download | yosys-74ef92b9c888fd05f03b4f679ecda6b04249e498.tar.gz yosys-74ef92b9c888fd05f03b4f679ecda6b04249e498.tar.bz2 yosys-74ef92b9c888fd05f03b4f679ecda6b04249e498.zip | |
Added "abc" label in synth script
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/synth.cc | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index c76b002cc..211b5905a 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -80,10 +80,12 @@ struct SynthPass : public Pass { log(" memory_map\n"); log(" opt -full\n"); log(" techmap\n"); - log(" opt -fast -full\n"); + log(" opt -fast\n"); #ifdef YOSYS_ENABLE_ABC + log("\n"); + log(" abc:\n"); log(" abc -fast\n"); - log(" opt_clean\n"); + log(" opt -fast\n"); #endif log("\n"); } @@ -150,12 +152,16 @@ struct SynthPass : public Pass { Pass::call(design, "memory_map"); Pass::call(design, "opt -full"); Pass::call(design, "techmap"); - Pass::call(design, "opt -fast -full"); - #ifdef YOSYS_ENABLE_ABC + Pass::call(design, "opt -fast"); + } + + #ifdef YOSYS_ENABLE_ABC + if (check_label(active, run_from, run_to, "abc")) + { Pass::call(design, "abc -fast"); - Pass::call(design, "opt_clean"); - #endif + Pass::call(design, "opt -fast"); } + #endif log_pop(); } |