| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | Add synth -keepdc option | Eddie Hung | 2019-07-08 | 1 | -2/+13 | |
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| * | | | mul2dsp to create cells that can be interchanged with $mul | Eddie Hung | 2019-07-18 | 1 | -1/+7 | |
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| * | | Make consistent | Eddie Hung | 2019-07-18 | 1 | -1/+2 | |
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| * | | Fix signed multiplier decomposition | Eddie Hung | 2019-07-18 | 1 | -29/+36 | |
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| * | | Working for unsigned | Eddie Hung | 2019-07-18 | 1 | -52/+28 | |
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| * | | Cleanup | Eddie Hung | 2019-07-18 | 1 | -70/+58 | |
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| * | | mul2dsp: Lower partial products always have unsigned inputs | David Shah | 2019-07-18 | 1 | -31/+41 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | Fix mul2dsp signedness | Eddie Hung | 2019-07-17 | 1 | -42/+38 | |
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| * | | A_SIGNED == B_SIGNED so flip both | Eddie Hung | 2019-07-17 | 1 | -21/+12 | |
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| * | | Add DSP_{A,B}_SIGNEDONLY macro | Eddie Hung | 2019-07-16 | 1 | -11/+40 | |
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| * | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 1 | -22/+26 | |
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| | * | | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH | David Shah | 2019-07-16 | 1 | -18/+22 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | mul2dsp: Fix indentation | David Shah | 2019-07-16 | 1 | -7/+7 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | Do not swap if equals | Eddie Hung | 2019-07-15 | 1 | -1/+1 | |
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| * | | | OUT port to Y in generic DSP | Eddie Hung | 2019-07-15 | 1 | -1/+1 | |
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| * | | Only swap if B_WIDTH > A_WIDTH | Eddie Hung | 2019-07-15 | 1 | -1/+1 | |
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| * | | Tidy up | Eddie Hung | 2019-07-15 | 1 | -39/+26 | |
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| * | | mul2dsp: Fix typo | David Shah | 2019-07-08 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | Add mul2dsp multiplier splitting rule and ECP5 mapping | David Shah | 2019-07-08 | 2 | -0/+238 | |
| |/ | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | Make doc consistent | Eddie Hung | 2019-06-14 | 1 | -1/+4 | |
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| * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-12 | 3 | -2/+182 | |
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| | * | Add "wreduce -keepdc", fixes #1016 | Clifford Wolf | 2019-05-20 | 1 | -2/+4 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 1 | -0/+2 | |
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| | | * | Run "peepopt" in generic "synth" pass and "synth_ice40" | Clifford Wolf | 2019-04-30 | 1 | -0/+2 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -2/+2 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -3/+4 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -0/+28 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵ | Clifford Wolf | 2019-04-23 | 1 | -70/+70 | |
| | | | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add $specify2 and $specify3 cells to simlib | Clifford Wolf | 2019-04-23 | 1 | -0/+147 | |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * / | synth to take -abc9 argument | Eddie Hung | 2019-02-20 | 1 | -5/+13 | |
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| * | Merge pull request #772 from whitequark/synth_lut | Clifford Wolf | 2019-01-02 | 1 | -6/+40 | |
| |\ | | | | | synth: add k-LUT mode | |||||
| | * | synth: add k-LUT mode. | whitequark | 2019-01-02 | 1 | -2/+36 | |
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| | * | synth: improve script documentation. NFC. | whitequark | 2019-01-02 | 1 | -6/+6 | |
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| * | | Merge pull request #771 from whitequark/techmap_cmp2lut | Clifford Wolf | 2019-01-02 | 2 | -1/+106 | |
| |\| | | | | | cmp2lut: new techmap pass | |||||
| | * | cmp2lut: new techmap pass. | whitequark | 2019-01-02 | 2 | -1/+106 | |
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| * | | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 2 | -2/+2 | |
| |/ | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | |||||
| * | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. | whitequark | 2018-12-05 | 2 | -0/+88 | |
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| * | Fix typo. | whitequark | 2018-12-05 | 1 | -2/+2 | |
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| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 2 | -8/+8 | |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | |||||
| * | Make -nordff the default in "prep" | Clifford Wolf | 2018-05-30 | 1 | -9/+13 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "synth -noshare" | Clifford Wolf | 2018-03-04 | 1 | -2/+11 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -0/+24 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix minor typo in "prep" help message | Clifford Wolf | 2017-12-19 | 1 | -1/+1 | |
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| * | Add dff2ff.v techmap file | Clifford Wolf | 2017-05-31 | 2 | -0/+15 | |
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| * | Add $_ANDNOT_ and $_ORNOT_ gates | Clifford Wolf | 2017-05-17 | 1 | -0/+38 | |
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| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -0/+16 | |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+8 | |
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| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 1 | -0/+12 | |
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| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 2 | -2/+23 | |
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| * | Added $ff and $_FF_ cell types | Clifford Wolf | 2016-10-12 | 2 | -1/+14 | |
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index : iCE40/yosys | |
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