| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Renamed stdcells_sim.v to simcells.v and fixed blackbox.v | Clifford Wolf | 2013-11-24 | 1 | -332/+0 |
| * | Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_ | Clifford Wolf | 2013-10-18 | 1 | -0/+166 |
| * | Moved common techlib files to techlibs/common | Clifford Wolf | 2013-09-15 | 1 | -0/+166 |
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index : iCE40/yosys | |
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