iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31	1	-785/+0
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*	Reorganized stdcells.v (no actual code change, just moved and indented stuff)	Clifford Wolf	2014-07-31	1	-747/+590
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*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	1	-2/+4
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*	New techmap default rules for $shr $sshr $shl $sshl	Clifford Wolf	2014-07-30	1	-282/+62
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-8/+64
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*	Fixes for improved techmap of shifts with large B inputs	Clifford Wolf	2014-03-06	1	-8/+8
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*	Strictly zero-extend unsigned A-inputs of shift operations in techmap	Clifford Wolf	2014-03-06	1	-4/+4
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*	Improved techmap of shift with wide B inputs	Clifford Wolf	2014-03-06	1	-13/+37
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+12
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*	Removed cases of trailing comma in stdcells.v	Clifford Wolf	2014-01-18	1	-3/+3
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*	Various small cleanups in stdcells.v techmap code	Clifford Wolf	2013-12-31	1	-68/+38
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*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28	1	-4/+10
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-0/+50
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*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24	1	-714/+40
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*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11	1	-41/+36
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*	Fixed techmap of $reduce_xnor with multi-bit outputs	Clifford Wolf	2013-11-07	1	-1/+7
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*	Fixed techmap of $gt and $ge with multi-bit outputs	Clifford Wolf	2013-11-06	1	-2/+14
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*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06	1	-11/+11
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*	Bugfix in dffsr techmap rules	Clifford Wolf	2013-10-18	1	-8/+8
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*	Added techmap rules for $sr, $dffsr and $dlatch	Clifford Wolf	2013-10-18	1	-0/+181
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*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15	1	-0/+1522