iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Removed cases of trailing comma in stdcells.v	Clifford Wolf	2014-01-18	1	-3/+3
*	Various small cleanups in stdcells.v techmap code	Clifford Wolf	2013-12-31	1	-68/+38
*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28	1	-4/+10
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-0/+50
*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24	1	-714/+40
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11	1	-41/+36
*	Fixed techmap of $reduce_xnor with multi-bit outputs	Clifford Wolf	2013-11-07	1	-1/+7
*	Fixed techmap of $gt and $ge with multi-bit outputs	Clifford Wolf	2013-11-06	1	-2/+14
*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06	1	-11/+11
*	Bugfix in dffsr techmap rules	Clifford Wolf	2013-10-18	1	-8/+8
*	Added techmap rules for $sr, $dffsr and $dlatch	Clifford Wolf	2013-10-18	1	-0/+181
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15	1	-0/+1522