| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | verilog: significant block scoping improvements | Zachary Snow | 2021-01-31 | 1 | -16/+13 |
| * | Add force_downto and force_upto wire attributes. | Marcelina Kościelnicka | 2020-05-19 | 1 | -0/+12 |
| * | techlibs/common: more robustness when *_WIDTH = 0 | Eddie Hung | 2020-05-05 | 1 | -2/+6 |
| * | cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp | Eddie Hung | 2020-04-03 | 1 | -1/+1 |
| * | cmp2lcu: fail if `LUT_WIDTH < 2 | Eddie Hung | 2020-04-03 | 1 | -1/+1 |
| * | +/cmp2lcu.v to work efficiently for fully/partially constant inputs | Eddie Hung | 2020-04-03 | 1 | -33/+42 |
| * | Refactor +/cmp2lcu.v into recursive techmap | Eddie Hung | 2020-04-03 | 1 | -38/+65 |
| * | Cleanup | Eddie Hung | 2020-04-03 | 1 | -31/+28 |
| * | Cleanup cmp2lcu.v | Eddie Hung | 2020-04-03 | 1 | -16/+16 |
| * | techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu | Eddie Hung | 2020-04-03 | 1 | -0/+83 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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