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* Add smtmap.v describing the smt2 backend's behavior for undef bitsJannis Harder2022-10-201-0/+1
* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-141-0/+2
* techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcuEddie Hung2020-04-031-0/+1
* Create +/abc9_model.v for $__ABC9_{DELAY,FF_}Eddie Hung2020-02-271-0/+1
* abc9_ops: -write_box is empty, output a dummy box to prevent ABC errorEddie Hung2020-01-151-1/+0
* Makefile: don't assume python is called `python3`Sean Cross2019-10-191-2/+2
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-051-0/+1
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| * Use a dummy box file if none specifiedEddie Hung2019-08-281-0/+1
* | Add mul2dsp multiplier splitting rule and ECP5 mappingDavid Shah2019-07-081-0/+1
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* cmp2lut: new techmap pass.whitequark2019-01-021-1/+1
* gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-051-0/+1
* Add dff2ff.v techmap fileClifford Wolf2017-05-311-0/+1
* Added "prep" commandClifford Wolf2015-10-141-0/+1
* Added first help messages for cell typesClifford Wolf2015-10-141-0/+15
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-121-7/+0
* Added cells.libClifford Wolf2015-01-161-0/+1
* Added add_share_file Makefile macroClifford Wolf2015-01-081-25/+6
* Fixed build with SMALL=1Clifford Wolf2014-12-301-0/+2
* Added "synth" commandClifford Wolf2014-09-141-0/+2
* Added adff2dff.v (for techmap -share_map)Clifford Wolf2014-08-071-1/+5
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-311-1/+5
* Added "make PRETTY=1"Clifford Wolf2014-07-241-10/+10
* Merged addition of SED makefile variable from github.com/Siesh1oo/yosysClifford Wolf2014-03-111-1/+1
* Added techlibs/common/pmux2mux.vClifford Wolf2014-01-171-1/+5
* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-241-3/+11
* Install simlib in datdirClifford Wolf2013-11-191-0/+6
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-151-0/+7