| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -1/+1 |
| * | anlogic: add latch cells | Icenowy Zheng | 2018-12-25 | 1 | -0/+12 |
| * | Merge pull request #752 from Icenowy/anlogic-lut-cost | Clifford Wolf | 2018-12-19 | 1 | -1/+1 |
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| | * | Anlogic: let LUT5/6 have more cost than LUT4- | Icenowy Zheng | 2018-12-19 | 1 | -1/+1 |
| * | | Merge pull request #753 from Icenowy/anlogic-makefile-fix | Clifford Wolf | 2018-12-19 | 1 | -0/+1 |
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| | * | | anlogic: fix Makefile.inc | Icenowy Zheng | 2018-12-19 | 1 | -0/+1 |
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| * / | anlogic: fix dbits of Anlogic Eagle DRAM16X4 | Icenowy Zheng | 2018-12-18 | 1 | -1/+1 |
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| * | anlogic: add support for Eagle Distributed RAM | Icenowy Zheng | 2018-12-17 | 4 | -1/+43 |
| * | Revert "Leave only real black box cells" | Icenowy Zheng | 2018-12-17 | 1 | -0/+312 |
| * | Leave only real black box cells | Miodrag Milanovic | 2018-12-02 | 1 | -312/+0 |
| * | Initial support for Anlogic FPGA | Miodrag Milanovic | 2018-12-01 | 7 | -0/+1590 |
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index : iCE40/yosys | |
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