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* Use C++11 final/override keywords.whitequark2020-06-183-8/+8
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-0/+10
| | | | Fixes #2058.
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-022-31/+31
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* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-0/+1
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* Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-025-10/+22
|\ | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys
| * Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-015-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
* | Merge pull request #1601 from YosysHQ/eddie/synth_retimeEddie Hung2020-01-021-2/+2
|\ \ | | | | | | "abc -dff" to no longer retime by default
| * | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
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| * | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
| |/ | | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* / Fix anlogic async flop mappingEddie Hung2020-01-011-8/+8
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* make note that it is for latch modeMiodrag Milanovic2019-09-181-0/+1
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* better lut handlingMiodrag Milanovic2019-09-181-4/+14
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* Added simulation models for Efinix and AnlogicMiodrag Milanovic2019-09-151-1/+79
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* Fix missing newline at end of fileClifford Wolf2019-08-221-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Proper arith for Anlogic and use standard passMiodrag Milanovic2019-08-125-91/+162
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* anlogic : Fix alu mappingMiodrag Milanovic2019-08-031-16/+8
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* Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-012-4/+4
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* Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-281-2/+2
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* Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
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* Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-026-2/+96
|\ | | | | anlogic: implement DRAM initialization
| * anlogic: implement DRAM initializationIcenowy Zheng2018-12-206-2/+96
| | | | | | | | | | | | | | | | | | | | | | As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-022-14/+15
|\ \ | | | | | | Initialization of Anlogic DFFs
| * | anlogic: set the init value of DFFsIcenowy Zheng2018-12-182-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As dffinit has already supported for different initialization strings for DFFs and check for re-initialization, initialization of Anlogic DFFs are now ready to go. Support for set the init values of Anlogic DFFs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* | | anlogic: add latch cellsIcenowy Zheng2018-12-251-0/+12
| |/ |/| | | | | | | | | | | Add latch cells to Anlogic cells replacement library by copying other FPGAs' latch code to it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Merge pull request #752 from Icenowy/anlogic-lut-costClifford Wolf2018-12-191-1/+1
|\ \ | | | | | | Anlogic: let LUT5/6 have more cost than LUT4-
| * | Anlogic: let LUT5/6 have more cost than LUT4-Icenowy Zheng2018-12-191-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s. So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost 2x resource of a LUT5. Change the -lut parameter passed to the abc command to pass this cost info to the ABC process. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Merge pull request #753 from Icenowy/anlogic-makefile-fixClifford Wolf2018-12-191-0/+1
|\ \ | | | | | | anlogic: fix Makefile.inc
| * | anlogic: fix Makefile.incIcenowy Zheng2018-12-191-0/+1
| |/ | | | | | | | | | | | | | | | | During the addition of DRAM inferring support, the installation of eagle_bb.v is accidentally removed. Fix this issue. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* / anlogic: fix dbits of Anlogic Eagle DRAM16X4Icenowy Zheng2018-12-181-1/+1
|/ | | | | | | | | The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM bits. Fix the dbits number in the RAM configuration. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* anlogic: add support for Eagle Distributed RAMIcenowy Zheng2018-12-174-1/+43
| | | | | | | | | | | | | The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Revert "Leave only real black box cells"Icenowy Zheng2018-12-171-0/+312
| | | | | | | | | | | This reverts commit 43030db5fff285de85096aaf5578b0548659f6b7. For a synthesis tool, generating EG_LOGIC cells are a good choice, as they can be furtherly optimized when PnR, although sometimes EG_LOGIC is not as blackbox as EG_PHY cells (because the latter is more close to the hardware implementation). Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Leave only real black box cellsMiodrag Milanovic2018-12-021-312/+0
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* Initial support for Anlogic FPGAMiodrag Milanovic2018-12-017-0/+1590
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