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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-01-25 19:25:25 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-01-25 19:25:25 +0100 |
| commit | 0de328da8ffea4902c52b286d7b38d67a714c742 (patch) | |
| tree | 3b54bf60d163f6b6d42407d55fdcf9fd271d6f63 /techlibs/anlogic | |
| parent | c4b61f2d69e88ddefd8ceec02ccf074c1b713004 (diff) | |
| download | yosys-0de328da8ffea4902c52b286d7b38d67a714c742.tar.gz yosys-0de328da8ffea4902c52b286d7b38d67a714c742.tar.bz2 yosys-0de328da8ffea4902c52b286d7b38d67a714c742.zip | |
Fixed Anlogic simulation model
Diffstat (limited to 'techlibs/anlogic')
| -rw-r--r-- | techlibs/anlogic/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v index 60a367928..058e76605 100644 --- a/techlibs/anlogic/cells_sim.v +++ b/techlibs/anlogic/cells_sim.v @@ -17,7 +17,7 @@ module AL_MAP_LUT1 ( ); parameter [1:0] INIT = 2'h0; parameter EQN = "(A)"; - assign Y = INIT >> A; + assign o = INIT >> a; endmodule module AL_MAP_LUT2 ( |