| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Revert "Leave only real black box cells" | Icenowy Zheng | 2018-12-17 | 1 | -0/+312 |
| * | Leave only real black box cells | Miodrag Milanovic | 2018-12-02 | 1 | -312/+0 |
| * | Initial support for Anlogic FPGA | Miodrag Milanovic | 2018-12-01 | 1 | -0/+1028 |
 |
index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
| aboutsummaryrefslogtreecommitdiffstats |