| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Harmonize BRAM/LUTRAM descriptions across all of Yosys. | whitequark | 2020-01-01 | 1 | -3/+3 |
| * | Proper arith for Anlogic and use standard pass | Miodrag Milanovic | 2019-08-12 | 1 | -1/+1 |
| * | anlogic: implement DRAM initialization | Icenowy Zheng | 2018-12-20 | 1 | -0/+2 |
| * | anlogic: fix Makefile.inc | Icenowy Zheng | 2018-12-19 | 1 | -0/+1 |
| * | anlogic: add support for Eagle Distributed RAM | Icenowy Zheng | 2018-12-17 | 1 | -1/+2 |
| * | Initial support for Anlogic FPGA | Miodrag Milanovic | 2018-12-01 | 1 | -0/+8 |
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index : iCE40/yosys | |
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