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* shregmap: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-39/+10
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* abc: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-25/+6
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* dffinit: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-41/+7
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* zinit: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-43/+11
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* dfflegalize: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-80/+25
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* clk2fflogic: Support all FF types.Marcelina Kościelnicka2020-07-241-200/+122
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* memory_dff: recognize more dff cellsMarcelina Kościelnicka2020-07-231-11/+112
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* techmap: Add _TECHMAP_CELLNAME_ special parameter.Marcelina Kościelnicka2020-07-211-0/+6
| | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.
* qbfsat: Add `-solver-option` option.Alberto Gonzalez2020-07-202-1/+15
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* opt_merge: Dedup one more use of FF cell type list.Marcelina Kościelnicka2020-07-151-3/+1
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* proc_dlatch: Remove init values for combinatorial processes.Marcelina Kościelnicka2020-07-121-0/+33
| | | | Fixes #2258.
* dfflegalize: Gather init values from all wires.Marcelina Kościelnicka2020-07-121-1/+1
| | | | Skipping non-selected wires is unsound in an obvious way.
* dfflibmap: Refactor to use dfflegalize internally.Marcelina Kościelnicka2020-07-091-211/+78
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* clkbufmap: improve input pad handling.Marcelina Kościelnicka2020-07-091-17/+39
| | | | | | - allow inserting only the input pad cell - do not insert the usual buffer if the input pad already acts as a buffer
* clk2fflogic: Consistently treat async control signals as negative hold.Marcelina Kościelnicka2020-07-091-57/+51
| | | | | | | This fixes some dfflegalize equivalence checks, and breaks others — and I strongly suspect the others are due to bad support for multiple async inputs in `proc` (in particular, lack of proper support for dlatchsr and sketchy circuits on dffsr control inputs).
* dfflegalize: Add special support for const-D latches.Marcelina Kościelnicka2020-07-091-0/+18
| | | | | | Those can be created by `opt_dff` when optimizing `$adff` with const clock, or with D == Q. Make dfflegalize do the opposite transform when such dlatches would be otherwise unimplementable.
* dfflegalize: typo fixMarcelina Kościelnicka2020-07-071-1/+1
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* Naming fixes.Marcelina Kościelnicka2020-07-052-2/+2
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* dfflegalize: Prefer mapping dff to sdff before adffMarcelina Kościelnicka2020-07-051-1/+1
| | | | | | This ensures that, when both sync and async FFs are available and abc9 is involved, the sync FFs will be used, and will thus remain available for sequential synthesis.
* opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.Marcelina Kościelnicka2020-07-051-0/+8
| | | | Fixes #2221.
* abc9: only techmap (* abc9_flop *) modulesEddie Hung2020-07-041-1/+1
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* abc9: techmap from user design to allow abc9_flop modules to be composedEddie Hung2020-07-041-1/+1
| | | | from other primitives
* Add newlines to help text for dfflegalizeRupert Swarbrick2020-07-031-11/+11
| | | | | | | | | | | | | I think these were probably missed by accident. Spotted because GCC spits out lots of messages like this: passes/techmap/dfflegalize.cc:114:7: warning: zero-length gnu_printf format string [-Wformat-zero-length] 114 | log(""); | ^~ (because we tell GCC that the first argument to log() looks like a printf control string in log.h, and a zero length such string triggers a warning).
* Merge pull request #2208 from boqwxp/qbfsat-cleanupclairexen2020-07-022-255/+273
|\ | | | | qbfsat: Cleanup and refactoring
| * qbfsat: Remove useless comment and #ifndef guards.Alberto Gonzalez2020-07-011-5/+0
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| * qbfsat: Specify default values for some options in the help message.Alberto Gonzalez2020-07-011-0/+2
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| * qbfsat: Clean up external executable command lines and update temporary ↵Alberto Gonzalez2020-07-011-3/+7
| | | | | | | | directory name.
| * qbfsat: Clean up and refactor data structures into `qbfsat.h`.Alberto Gonzalez2020-07-012-248/+265
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* | Merge pull request #2186 from YosysHQ/mwk/dfflegalizeclairexen2020-07-022-0/+1357
|\ \ | | | | | | Add dfflegalize pass.
| * | Add dfflegalize pass.Marcelina Kościelnicka2020-07-012-0/+1357
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* | | Merge pull request #2211 from YosysHQ/mwk/fix-fmcombine-ffclairexen2020-07-021-2/+1
|\ \ \ | | | | | | | | fmcombine: use the master ff cell type list
| * | | fmcombine: use the master ff cell type listMarcelina Kościelnicka2020-06-301-2/+1
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* | | Merge pull request #2210 from YosysHQ/mwk/fix-opt_mergeclairexen2020-07-021-3/+1
|\ \ \ | |_|/ |/| | opt_merge: use the master FF type list
| * | opt_merge: use the master FF type listMarcelina Kościelnicka2020-06-301-3/+1
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* | Merge pull request #2138 from boqwxp/qbfsat-oflagclairexen2020-07-011-16/+47
|\ \ | | | | | | qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC
| * | qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC.Alberto Gonzalez2020-06-301-16/+47
| | | | | | | | | | | | | | | | | | Thanks to @mwk for the gate mapping part of the ABC scripts. Co-Authored-By: Marcelina Kościelnicka <mwk@0x04.net>
* | | Merge pull request #2206 from boqwxp/qbfsat-fix-name-specializationclairexen2020-07-011-2/+24
|\ \ \ | | | | | | | | qbfsat: Fix name-based hole specialization
| * | | qbfsat: Fix name-based hole specialization.Alberto Gonzalez2020-06-301-2/+24
| |/ / | | | | | | | | | Look for unique connections in the containing module with the $anyconst port Y SigBit on the RHS and use those. If no such connection is found, fall back to using the name of the $anyconst port Y SigBit.
* | | Merge pull request #2199 from YosysHQ/mmicko/sim_memoryclairexen2020-06-301-1/+4
|\ \ \ | | | | | | | | sim - error when memrd and memwr detected
| * | | sim - error when memrd and memwr detectedMiodrag Milanovic2020-06-291-1/+4
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* | | | Merge pull request #2201 from YosysHQ/fix_test_cell_ilangclairexen2020-06-301-2/+2
|\ \ \ \ | |_|_|/ |/| | | Use ID macro to fix assertion
| * | | Use ID macro to fix assertionMiodrag Milanovic2020-06-291-2/+2
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* | / techmap: don't drop attributes on replaced cells.whitequark2020-06-291-2/+3
| |/ |/| | | | | | | | | This was introduced in 76c4ee4ea5cb6a3dc214f66237af22a1bedda010. Fixes #2204.
* | Merge pull request #2200 from YosysHQ/mmicko/fix_exposeMiodrag Milanović2020-06-291-7/+23
|\ \ | | | | | | expose pass fix
| * | Give error that options are exclusiveMiodrag Milanovic2020-06-291-2/+6
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| * | cleanupMiodrag Milanovic2020-06-291-12/+13
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| * | expose pass fixMiodrag Milanovic2020-06-291-5/+16
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* / test_cell: don't generate directional shifts with \B_SIGNED=1Xiretza2020-06-281-0/+4
|/ | | | | This was made an explicit error in e97e33d, "kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.".
* Merge pull request #2168 from whitequark/assert-unused-exprsclairexen2020-06-255-20/+20
|\ | | | | Use (and ignore) the expression provided to log_assert in NDEBUG builds
| * Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused).whitequark2020-06-191-10/+10
| | | | | | | | | | [[maybe_unused]] is available since C++17, so this commit adds a polyfill YS_MAYBE_UNUSED. Once we require C++17 we can drop it.
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