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* Use new read_id_num helper function elsewhere in hierarchy.ccRupert Swarbrick2021-07-201-5/+6
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* Extract connection checking logic from expand_module in hierarchy.ccRupert Swarbrick2021-07-201-23/+64
| | | | | No functional change, but pulls more logic out of the expand_module function.
* Extract missing module support in hierarchy.cc to a helper functionRupert Swarbrick2021-07-141-44/+68
| | | | | | | | | | I think the code is now a bit easier to follow (and has lost some levels of indentation!). The only non-trivial change is that I removed the check for cell->type[0] != '$' when deciding whether to complain if we couldn't find a module. This will always be true because of the early exit earlier in the function.
* Delete unused found_init variableRupert Swarbrick2021-07-141-3/+0
| | | | | | | Spotted during compilation: passes/proc/proc_init.cc: In function ‘void {anonymous}::proc_init(Yosys::RTLIL::Module*, Yosys::SigMap&, Yosys::RTLIL::Process*)’: passes/proc/proc_init.cc:31:7: warning: variable ‘found_init’ set but not used [-Wunused-but-set-variable]
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-123-16/+12
| | | | | | - add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
* Move interface expansion in hierarchy.cc into a helper classRupert Swarbrick2021-06-161-100/+189
| | | | | | | | | | | | There should be no functional change, but this splits up the control flow across functions, using class fields to hold the state that's being tracked. The result should be a bit easier to read. This is part of work to add bind support, but I'm doing some refactoring in the hierarchy pass to make the code a bit easier to work with. The idea is that (eventually) the IFExpander object will hold all the logic for expanding interfaces, and then other code can do bind insertion.
* opt_muxtree: Update port_off and port_idx even for constant bitsgatecat2021-06-111-17/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-091-122/+85
| | | | | The previous code, in addition to being needlessly limitted to 32 bits in the first place, also had UB for the 31th bit (doing 1 << 31).
* opt_expr: Optimize div/mod by const 1.Marcelina Kościelnicka2021-06-091-4/+4
| | | | | | | | Turns out the code for div by a power of 2 is already almost capable of optimizing this to a shift-by-0 or and-with-0, which will be further folded into nothingness; let's beef it up to handle div by 1 as well. Fixes #2820.
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-09149-154/+154
|\ | | | | Fixing old e-mail addresses and deadnames
| * Fix deadname SVN linksClaire Xenia Wolf2021-06-092-3/+3
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-091-1/+1
| | | | | | | | | | | | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-08149-151/+151
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* | autoname: simple perf optimizationsZachary Snow2021-06-081-11/+15
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* memory_map: Improve start_offset handling.Marcelina Kościelnicka2021-05-311-35/+31
| | | | Fixes #2775.
* memory_share: Add read port merging.Marcelina Kościelnicka2021-05-291-0/+140
| | | | | This is mostly meant for wide port recognition, but may also happen to merge some ports with compatible initial/reset values (eg. 0 vs x).
* memory_share: Improve sat-based port sharing.Marcelina Kościelnicka2021-05-281-117/+151
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* Make a few passes auto-call Mem::narrow instead of rejecting wide ports.Marcelina Kościelnicka2021-05-281-14/+1
| | | | | | This essentially adds wide port support for free in passes that don't have a usefully better way of handling wide ports than just breaking them up to narrow ports, avoiding "please run memory_narrow" annoyance.
* memory_share: Improve same-address merging, recognize wide write ports.Marcelina Kościelnicka2021-05-271-204/+77
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* kernel/mem: Add sub_addr helpers.Marcelina Kościelnicka2021-05-261-6/+2
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* mem/extract_rdff: Fix "no FF made" edge case.Marcelina Kościelnicka2021-05-251-2/+5
| | | | | | | When converting a sync transparent read port with const address to async read port, nothing at all needs to be done other than clk_enable change, and thus we have no FF cell to return. Handle this case correctly in the helper and in its users.
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-251-23/+38
| | | | | Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
* opt_mem: Add reset/init value support.Marcelina Kościelnicka2021-05-251-0/+12
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* memory_bram: Respect write port priority.Marcelina Kościelnicka2021-05-251-0/+14
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* opt_mem_feedback: Respect write port priority.Marcelina Kościelnicka2021-05-251-0/+15
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* Add memory_narrow pass.Marcelina Kościelnicka2021-05-252-0/+68
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* memory_share: Add wide port support.Marcelina Kościelnicka2021-05-251-0/+6
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* opt_mem_feedback: Add wide port support.Marcelina Kościelnicka2021-05-251-14/+24
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* memory_map: Add wide port support.Marcelina Kościelnicka2021-05-251-16/+17
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* sim: Add wide port support.Marcelina Kościelnicka2021-05-251-3/+3
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* Reject wide ports in some passes that will never support them.Marcelina Kościelnicka2021-05-251-0/+14
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* opt_mem_feedback: Rewrite feedback path finding logic.Marcelina Kościelnicka2021-05-241-115/+130
| | | | Fixes #2766.
* opt_mem_feedback: Convert to Mem helpers.Marcelina Kościelnicka2021-05-241-49/+28
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* memory_share: Use Mem helpers.Marcelina Kościelnicka2021-05-231-89/+71
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* extract_rdff: Add initvals parameter.Marcelina Kościelnicka2021-05-232-9/+15
| | | | | This is not used yet, but will be needed when read port reset/initial value support lands.
* memory_share: Split off feedback path finding as a separate pass.Marcelina Kościelnicka2021-05-234-242/+343
| | | | | memory_share is actually three passes in a trenchcoat. Split off the one that has the least in common with the other two as a separate pass.
* Add new helper class for merging FFs into cells, use for memory_dff.Marcelina Kościelnicka2021-05-231-237/+104
| | | | Fixes #1854.
* opt_mem: Remove write ports with const-0 EN.Marcelina Kościelnicka2021-05-231-0/+12
| | | | Fixes #2765.
* memory_memx: Use Mem helper.Marcelina Kościelnicka2021-05-221-42/+31
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* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-225-24/+7
| | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list.
* memory_dff: Use Mem helper.Marcelina Kościelnicka2021-05-211-19/+26
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* connect: Add -assert option, fix non-working sigmap.Marcelina Kościelnicka2021-05-081-4/+24
| | | | Should be useful for writing tests.
* opt_dff: Fix NOT gates wired in reverse.Marcelina Kościelnicka2021-05-041-2/+2
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* flatten: rewrite memid in memwr actions.whitequark2021-04-091-0/+3
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* equiv: Suggest running async2sync or clk2fflogic where appropriate.Marcelina Kościelnicka2021-03-302-3/+10
| | | | See #2713.
* abc9: uniquify blackboxes like whiteboxes (#2695)Eddie Hung2021-03-291-10/+6
| | | | | | | | | * abc9_ops: uniquify blackboxes too * abc9_ops: update comment * abc9_ops: allow bypass for param-less blackboxes * Add tests
* abc9: fix SCC issues (#2694)Eddie Hung2021-03-292-28/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
* Clarify bugpoint documentation regarding outputIris Johnson2021-03-241-0/+2
| | | | | | | Bugpoint's current documentation does specify that the result of a run is stored as the current design, however it's easy to skim over what that means in practice. Add a documentation comment to explain specifically that an after bugpoint `write_xyz` pass is required to save the reduced design.
* bugpoint: add runner optionZachary Snow2021-03-171-6/+17
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* blackbox: Include whiteboxed modulesgatecat2021-03-171-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
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