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authorMarcelina Koƛcielnicka <mwk@0x04.net>2021-05-25 18:49:17 +0200
committerMarcelina Koƛcielnicka <mwk@0x04.net>2021-05-25 20:06:00 +0200
commite6b078d156f8690ab06d342da9be9af02cbcc3aa (patch)
tree2810bb75465adc5324b2027bf43e1b306d25b001 /passes
parent24b880b2de1676b420f5a0bbdf3805dab38b8f00 (diff)
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opt_mem: Add reset/init value support.
Diffstat (limited to 'passes')
-rw-r--r--passes/opt/opt_mem.cc12
1 files changed, 12 insertions, 0 deletions
diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc
index 0409fb736..2788648ec 100644
--- a/passes/opt/opt_mem.cc
+++ b/passes/opt/opt_mem.cc
@@ -51,6 +51,8 @@ struct OptMemPass : public Pass {
int total_count = 0;
for (auto module : design->selected_modules()) {
+ SigMap sigmap(module);
+ FfInitVals initvals(&sigmap, module);
for (auto &mem : Mem::get_selected_memories(module)) {
bool changed = false;
for (auto &port : mem.wr_ports) {
@@ -65,6 +67,16 @@ struct OptMemPass : public Pass {
}
if (mem.wr_ports.empty() && mem.inits.empty()) {
+ // The whole memory array will contain
+ // only State::Sx, but the embedded read
+ // registers could have reset or init values.
+ // They will probably be optimized away by
+ // opt_dff later.
+ for (int i = 0; i < GetSize(mem.rd_ports); i++) {
+ mem.extract_rdff(i, &initvals);
+ auto &port = mem.rd_ports[i];
+ module->connect(port.data, Const(State::Sx, GetSize(port.data)));
+ }
mem.remove();
total_count++;
}