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* Fixes for some of clang scan-build detected issuesMiodrag Milanovic2023-01-174-2/+9
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* Merge pull request #3605 from gadfort/stat-json-areaN. Engelhardt2023-01-111-0/+3
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| * stat: ensure area is included in json outputPeter Gadfort2022-12-291-0/+3
| | | | | | | | Signed-off-by: Peter Gadfort <peter.gadfort@gmail.com>
* | Merge branch 'master' into claire/eqystuffClaire Xen2023-01-114-36/+36
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| * \ Merge pull request #3537 from jix/xpropJannis Harder2023-01-1110-35/+1508
| |\ \ | | | | | | | | New xprop pass
| * | | Deprecate gcc-4.8Miodrag Milanovic2023-01-114-36/+36
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* | | | Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuffClaire Xenia Wolf2023-01-115-5/+25
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| * | | qbfsat support for cvc5, fixes #3608Miodrag Milanovic2023-01-092-3/+7
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| * | formalff: Proper error messages on async inputs for the -clk2ff modeJannis Harder2022-12-091-0/+3
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| * | stat: Fix JSON output for empty designsJannis Harder2022-12-021-2/+2
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| * | tee: Allow logging command output to a given scratchpad valueJannis Harder2022-12-021-0/+13
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* | | Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuffClaire Xenia Wolf2022-12-211-14/+10
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| * | | xprop: Improve signal splitting codeJannis Harder2022-12-121-14/+10
| | | | | | | | | | | | | | | | | | | | Avoid splitting output ports twice when combining -split-outputs with -split-public and clean up the corresponding code.
* | | | Allow non-unique modules without state in sim writeback-modeClaire Xenia Wolf2022-12-211-4/+5
| | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | Small bugfix in uniquify passClaire Xenia Wolf2022-12-211-0/+1
|/ / / | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Improvements in "viz" passClaire Xenia Wolf2022-12-091-24/+100
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Add gold-x handing to miter cross port handlingClaire Xenia Wolf2022-12-081-1/+9
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuffClaire Xenia Wolf2022-12-081-0/+39
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| * | | xprop: Add -split-public optionJannis Harder2022-12-081-0/+39
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* | | | Improvements in "viz" commandClaire Xenia Wolf2022-12-071-17/+51
|/ / / | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Improvements in "viz" passClaire Xenia Wolf2022-12-071-313/+453
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Various improvements in "viz" commandClaire Xenia Wolf2022-12-061-72/+242
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Bugfix in splitcells passClaire Xenia Wolf2022-12-061-5/+13
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Improvements in "viz" commandClaire Xenia Wolf2022-12-041-45/+196
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Add "viz" pass for visualizing big-picture data flow in larger designsClaire Xenia Wolf2022-12-042-0/+511
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Add splitcells passClaire Xenia Wolf2022-12-042-0/+192
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Merge branch 'xprop' of github.com:jix/yosys into claire/eqystuffClaire Xenia Wolf2022-12-0110-35/+1508
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| * | miter: Add -make_cover option to cover each output pair differenceJannis Harder2022-11-301-0/+14
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| * | formalff: Fix -ff2anyinit assertion error for fine FFsJannis Harder2022-11-301-0/+2
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| * | New xprop pass to encode 3-valued x-propagation using 2-valued logicJannis Harder2022-11-302-0/+1199
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| * | sim: Improved global clock handlingJannis Harder2022-11-301-13/+14
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| * | opt_expr: Optimizations for `$bweqx` and `$bwmux`Jannis Harder2022-11-301-0/+63
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| * | Add bwmuxmap passJannis Harder2022-11-302-0/+71
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| * | Add bitwise `$bweqx` and `$bwmux` cellsJannis Harder2022-11-302-6/+29
| | | | | | | | | | | | | | | | | | The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals.
| * | opt_expr: Fix shift/shiftx optimizationsJannis Harder2022-11-301-3/+3
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| * | opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cellsJannis Harder2022-11-291-0/+33
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| * | opt_expr: Optimize bitwise logic ops with one fully const inputJannis Harder2022-11-291-0/+81
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| * | simplemap: Map `$xnor` to `$_XNOR_` cellsJannis Harder2022-11-291-15/+1
| |/ | | | | | | | | The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of the `$_XNOR_` cell.
* / Add insbuf -chain modeClaire Xenia Wolf2022-12-011-2/+38
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* sat: Add -set-def-formal option to force defined $any* outputsJannis Harder2022-11-281-6/+22
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* Support importing verilog configurations using VerificMiodrag Milanovic2022-11-251-1/+1
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* mention prerequisites in fsm_detect and fsm helpN. Engelhardt2022-11-212-0/+18
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* Rst docs conversion (#3496)KrystalDelusion2022-11-152-1/+3
| | | Rst docs conversion
* sim: Run a comb-only update step to set past values during FST cosimJannis Harder2022-11-071-12/+11
| | | | | | | | The previous approach only initialized past_d and past_ad while for FST cosim we also need to initialize the other past values like past_clk, etc. Also to properly initialize them, we need to run a combinational update step in case any of the wires feeding into the FF are private or otherwise not part of the FST.
* Add extra time at the end of a sat VCD traceClaire Xenia Wolf2022-11-011-0/+1
| | | | | | | Otherwise the final values will not show up in gtkwave waveforms when looking at the generated traces. Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Add miter -cross optionClaire Xenia Wolf2022-10-241-4/+32
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* Consistent $mux undef handlingJannis Harder2022-10-241-1/+1
| | | | | | | | | | | | | | | | | | | * Change simlib's $mux cell to use the ternary operator as $_MUX_ already does * Stop opt_expr -keepdc from changing S=x to S=0 * Change const eval of $mux and $pmux to match the updated simlib (fixes sim) * The sat behavior of $mux already matches the updated simlib The verilog frontend uses $mux for the ternary operators and this changes all interpreations of the $mux cell (that I found) to match the verilog simulation behavior for the ternary operator. For 'if' and 'case' expressions the frontend may also use $mux but uses $eqx if the verilog simulation behavior is requested with the '-ifx' option. For $pmux there is a remaining mismatch between the sat behavior and the simlib behavior. Resolving this requires more discussion, as the $pmux cell does not directly correspond to a specific verilog construct.
* Add "check -assert" to equiv_optClaire Xenia Wolf2022-10-071-1/+13
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Exclude primary inputs from quiv_make rewiringClaire Xenia Wolf2022-10-071-0/+7
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Revert "Merge pull request #641 from tklam/master"Claire Xenia Wolf2022-10-071-81/+5
| | | | | | | | | | This reverts commit 08be796cb8b1890923e459cda92211fda763f0c1, reversing changes made to 38dbb44fa0815b1fe80e68e17798aaa341d998cd. This fixes #2728. PR #641 did not actually "fix" #639. The actual issue in #639 is not equiv_make, but assumptions in equiv_simple that are not true for the test case provided in #639.
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