| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Rip out all non FPGA stuff from abc9 | Eddie Hung | 2019-06-12 | 1 | -343/+111 |
| * | Fix spelling | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
| * | Revert "For 'stat' do not count modules with abc_box_id" | Eddie Hung | 2019-06-12 | 1 | -3/+0 |
| * | Be more precise when connecting during ABC9 re-integration | Eddie Hung | 2019-06-12 | 1 | -1/+3 |
| * | Remove hacky wideports_split from abc9 | Eddie Hung | 2019-06-12 | 1 | -52/+4 |
| * | Fix compile errors when #if 1 for debug | Eddie Hung | 2019-06-12 | 1 | -7/+8 |
| * | Do not call abc9 if no outputs | Eddie Hung | 2019-06-12 | 1 | -54/+65 |
| * | More write_xaiger cleanup | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
| * | Consistency | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
| * | Merge branch 'xc7mux' into xaig | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
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| | * | Typo: wire delay is -W argument | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
| * | | Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7... | Eddie Hung | 2019-06-12 | 1 | -6/+3 |
| * | | Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" | Eddie Hung | 2019-06-12 | 2 | -267/+0 |
| * | | Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" | Eddie Hung | 2019-06-12 | 1 | -14/+10 |
| * | | Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx" | Eddie Hung | 2019-06-12 | 1 | -5/+13 |
| * | | Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx" | Eddie Hung | 2019-06-12 | 1 | -13/+5 |
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| * | Add "-W' wire delay arg to abc9, use from synth_xilinx | Eddie Hung | 2019-06-11 | 1 | -5/+13 |
| * | Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7... | Eddie Hung | 2019-06-11 | 1 | -15/+10 |
| * | Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux | Eddie Hung | 2019-06-11 | 1 | -10/+15 |
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| | * | Try way that doesn't involve creating a new wire | Eddie Hung | 2019-06-11 | 1 | -10/+15 |
| * | | Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux | Eddie Hung | 2019-06-10 | 1 | -3/+6 |
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| | * | If d_bit already in sigbit_chain_next, create extra wire | Eddie Hung | 2019-06-10 | 1 | -3/+6 |
| | * | Allow muxcover costs to be changed | Eddie Hung | 2019-06-07 | 1 | -12/+42 |
| * | | Revert "Rename shregmap -tech xilinx -> xilinx_dynamic" | Eddie Hung | 2019-06-10 | 1 | -4/+4 |
| * | | Revert "shregmap -tech xilinx_dynamic to work -params and -enpol" | Eddie Hung | 2019-06-10 | 1 | -26/+6 |
| * | | Revert "Refactor to ShregmapTechXilinx7Static" | Eddie Hung | 2019-06-10 | 1 | -86/+46 |
| * | | Revert "Add -tech xilinx_static" | Eddie Hung | 2019-06-10 | 1 | -13/+2 |
| * | | Revert "Continue support for ShregmapTechXilinx7Static" | Eddie Hung | 2019-06-10 | 1 | -81/+30 |
| * | | Revert "shregmap -tech xilinx_static to handle INIT" | Eddie Hung | 2019-06-10 | 1 | -32/+22 |
| * | | Fine tune aigerparse | Eddie Hung | 2019-06-07 | 1 | -1/+5 |
| * | | Allow muxcover costs to be changed | Eddie Hung | 2019-06-07 | 1 | -12/+42 |
| * | | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux | Eddie Hung | 2019-06-06 | 1 | -10/+14 |
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| | * | | Fix and test for balanced case | Eddie Hung | 2019-06-06 | 1 | -10/+14 |
| * | | | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux | Eddie Hung | 2019-06-06 | 5 | -2/+277 |
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| | * | | Support cascading $pmux.A with $mux.A and $mux.B | Eddie Hung | 2019-06-06 | 1 | -17/+25 |
| | * | | More cleanup | Eddie Hung | 2019-06-06 | 1 | -15/+20 |
| | * | | Fix spacing | Eddie Hung | 2019-06-06 | 1 | -6/+5 |
| | * | | Non chain user check using next_sig | Eddie Hung | 2019-06-06 | 1 | -7/+5 |
| | * | | Move muxpack from passes/techmap to passes/opt | Eddie Hung | 2019-06-06 | 3 | -1/+1 |
| | * | | Update doc | Eddie Hung | 2019-06-06 | 1 | -4/+5 |
| | * | | Add tests, fix for != | Eddie Hung | 2019-06-06 | 1 | -9/+32 |
| | * | | Missing file | Eddie Hung | 2019-06-06 | 1 | -0/+232 |
| | * | | Initial adaptation of muxpack from shregmap | Eddie Hung | 2019-06-06 | 1 | -0/+1 |
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| | * | Merge pull request #1071 from YosysHQ/eddie/fix_1070 | Clifford Wolf | 2019-06-06 | 1 | -2/+2 |
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| | | * | Fix typo in opt_rmdff | Eddie Hung | 2019-06-05 | 1 | -2/+2 |
| | * | | Merge pull request #1072 from YosysHQ/eddie/fix_1069 | Clifford Wolf | 2019-06-06 | 1 | -0/+5 |
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| | | * | | Error out if no top module given before 'sim' | Eddie Hung | 2019-06-05 | 1 | -0/+5 |
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| | * / | Missing doc for -tech xilinx in shregmap | Eddie Hung | 2019-06-05 | 1 | -0/+3 |
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| | * | Merge pull request #1067 from YosysHQ/clifford/fix1065 | Eddie Hung | 2019-06-05 | 1 | -1/+1 |
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| * | | | shregmap -tech xilinx_static to handle INIT | Eddie Hung | 2019-06-05 | 1 | -22/+32 |
