| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | More cleanup | Eddie Hung | 2019-08-28 | 1 | -12/+14 |
| * | More cleanup | Eddie Hung | 2019-08-28 | 1 | -9/+6 |
| * | Do not use default_params dict, hardcode default values, cleanup | Eddie Hung | 2019-08-28 | 2 | -25/+21 |
| * | Always generate if no match | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
| * | Rename test_pmgen arg xilinx_srl.{fixed,variable} | Eddie Hung | 2019-08-28 | 1 | -2/+2 |
| * | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-28 | 5 | -89/+457 |
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| | * | Fix typo | Clifford Wolf | 2019-08-28 | 1 | -2/+2 |
| | * | Add "paramap" pass | Clifford Wolf | 2019-08-28 | 1 | -67/+118 |
| | * | Merge pull request #1325 from YosysHQ/eddie/sat_init | Clifford Wolf | 2019-08-28 | 1 | -1/+1 |
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| | | * | Ignore all 1'bx in (* init *) | Eddie Hung | 2019-08-27 | 1 | -3/+1 |
| | | * | In sat: 'x' in init attr should not override constant | Eddie Hung | 2019-08-22 | 1 | -0/+2 |
| | * | | improve clkbuf_inhibit propagation upwards through hierarchy | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+12 |
| | * | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 4 | -32/+279 |
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| | | * | | indo -> into | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
| | * | | | clkbufmap to only check clkbuf_inhibit if no selection given | Eddie Hung | 2019-08-23 | 1 | -5/+18 |
| | * | | | Review comment from @cliffordwolf | Eddie Hung | 2019-08-23 | 1 | -1/+2 |
| | * | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 48 | -768/+2262 |
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| | * | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-16 | 41 | -2157/+2152 |
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| | * | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 2 | -28/+9 |
| | * | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 2 | -29/+4 |
| | * | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 3 | -20/+356 |
| * | | | | | Missing close bracket | Eddie Hung | 2019-08-26 | 1 | -1/+1 |
| * | | | | | Revert "In sat: 'x' in init attr should not override constant" | Eddie Hung | 2019-08-26 | 1 | -2/+0 |
| * | | | | | Remove leftover header | Eddie Hung | 2019-08-26 | 1 | -1/+0 |
| * | | | | | Improve xilinx_srl.fixed generate, add .variable generate | Eddie Hung | 2019-08-26 | 1 | -26/+75 |
| * | | | | | Account for maxsubcnt overflowing | Eddie Hung | 2019-08-26 | 1 | -1/+1 |
| * | | | | | Add xilinx_srl_pm.variable to test_pmgen | Eddie Hung | 2019-08-26 | 1 | -0/+2 |
| * | | | | | Populate generate for xilinx_srl.fixed pattern | Eddie Hung | 2019-08-26 | 1 | -22/+54 |
| * | | | | | Add xilinx_srl_fixed, fix typos | Eddie Hung | 2019-08-26 | 1 | -2/+6 |
| * | | | | | Create new $__XILINX_SHREG_ cell for variable length too | Eddie Hung | 2019-08-23 | 1 | -31/+30 |
| * | | | | | Do not allow Q of last cell of variable length SRL to be (* keep *) | Eddie Hung | 2019-08-23 | 1 | -0/+1 |
| * | | | | | Also add first.Q to chain_bits since variable length | Eddie Hung | 2019-08-23 | 1 | -0/+1 |
| * | | | | | Do not enforce !EN_POLARITY on $dffe | Eddie Hung | 2019-08-23 | 1 | -2/+0 |
| * | | | | | Create new cell for fixed length SRL | Eddie Hung | 2019-08-23 | 1 | -14/+22 |
| * | | | | | Cleanup FDRE matching | Eddie Hung | 2019-08-23 | 1 | -45/+19 |
| * | | | | | Oops don't need a finally block | Eddie Hung | 2019-08-23 | 1 | -5/+0 |
| * | | | | | Keep track of bits in variable length chain, to check for taps | Eddie Hung | 2019-08-23 | 1 | -0/+12 |
| * | | | | | Don't forget $dff has no EN | Eddie Hung | 2019-08-23 | 1 | -2/+4 |
| * | | | | | Same for variable length | Eddie Hung | 2019-08-23 | 1 | -2/+10 |
| * | | | | | Filter on en_port for fixed length | Eddie Hung | 2019-08-23 | 1 | -4/+24 |
| * | | | | | Check clock is consistent | Eddie Hung | 2019-08-23 | 1 | -5/+25 |
| * | | | | | Fix last_cell.D | Eddie Hung | 2019-08-23 | 1 | -2/+1 |
| * | | | | | Revert "Add a unique argument to pmgen's nusers()" | Eddie Hung | 2019-08-23 | 1 | -8/+4 |
| * | | | | | Revert "Fix polarity" | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
| * | | | | | Fix polarity | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
| * | | | | | Check for non unique nusers/fanouts | Eddie Hung | 2019-08-23 | 1 | -2/+2 |
| * | | | | | Add a unique argument to pmgen's nusers() | Eddie Hung | 2019-08-23 | 1 | -4/+8 |
| * | | | | | Update doc | Eddie Hung | 2019-08-23 | 1 | -12/+19 |
| * | | | | | Remove (* init *) entry when consumed into SRL | Eddie Hung | 2019-08-23 | 1 | -2/+6 |
| * | | | | | indo -> into | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
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index : iCE40/yosys | |
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