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* Added correct RTL undef handling to eval vloghammer modeClifford Wolf2013-11-061-3/+17
* Added eval -vloghammer_report modeClifford Wolf2013-11-061-4/+142
* Added support for "keep" attributes on wiresClifford Wolf2013-11-051-0/+5
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-11-031-0/+57
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| * Added resolution of positional arguments to hierarchy passClifford Wolf2013-11-031-0/+57
* | Added placeholder check to dfflibmap and cleaned up some other placeholder ch...Clifford Wolf2013-10-312-3/+3
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* Added detection for endless recursion in fsm_detect passClifford Wolf2013-10-301-4/+15
* Fixed help message typo (memory pass)Clifford Wolf2013-10-301-1/+1
* Added -format option to splitnetsClifford Wolf2013-10-291-1/+16
* Added support for i/o buffers to iopadmapClifford Wolf2013-10-261-10/+35
* Added support for sr flip-flops to dfflibmapClifford Wolf2013-10-241-3/+168
* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-241-4/+115
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-245-7/+7
* Improved handling of dff with async resetsClifford Wolf2013-10-211-5/+60
* Added handling of multiple async paths in proc_arstClifford Wolf2013-10-192-8/+21
* Added dffsr support to proc_dff passClifford Wolf2013-10-181-7/+72
* Improved way of connecting ports in techmap passClifford Wolf2013-10-171-18/+36
* Only prefer connected signals iff they have public namesClifford Wolf2013-10-171-5/+6
* Fixed bug in synthesis of memories that are never writtenClifford Wolf2013-10-171-2/+7
* Avoid re-arranging signals on register outputsClifford Wolf2013-10-171-3/+31
* Fixed detection of major wires in opt_cleanClifford Wolf2013-10-171-0/+3
* Added iopadmap passClifford Wolf2013-10-163-1/+161
* Moved dfflibmap from passes/dfflibmap to passes/techmapClifford Wolf2013-10-166-11/+10
* Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";'Clifford Wolf2013-10-161-1/+4
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-151-1/+1
* Some minor documentation fixesClifford Wolf2013-08-212-2/+2
* Minor fixes in abc build instructions and abc passClifford Wolf2013-08-201-4/+4
* Added sat -ignore_div_by_zero switchClifford Wolf2013-08-151-1/+11
* Added eval -brute_force_equiv_checker_x modeClifford Wolf2013-08-151-5/+15
* Added "clean -purge" and ";;;" supportClifford Wolf2013-08-111-4/+19
* Added ";;" as shortcut for "; clean;"Clifford Wolf2013-08-111-0/+3
* freduce performance fixClifford Wolf2013-08-101-4/+8
* Added techmap -opt modeClifford Wolf2013-08-091-7/+39
* Some fixes to improve determinismClifford Wolf2013-08-093-30/+33
* Sort ctrl signals in fsm_extractClifford Wolf2013-08-081-0/+3
* Added -try option to freduce passClifford Wolf2013-08-081-16/+44
* Added "clean" command (less verbose opt_clean)Clifford Wolf2013-08-081-9/+52
* Fixed topological ordering in freduce passClifford Wolf2013-08-071-54/+67
* Improved handling of private names in opt_clean and rename commandsClifford Wolf2013-08-072-7/+39
* Small bugfixes in freduce passClifford Wolf2013-08-061-4/+14
* Added freduce commandClifford Wolf2013-08-062-0/+362
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-272-0/+129
* Automatically run "proc" on extract map filesClifford Wolf2013-07-241-0/+5
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-234-14/+255
* Bugfixes for empty signal vectorsClifford Wolf2013-07-101-0/+3
* Added opt_clean -purge optionClifford Wolf2013-07-071-7/+19
* Fixed handling of $eq and $ne in opt_constClifford Wolf2013-07-071-2/+2
* Added SAT support for -all/-max with -verifyClifford Wolf2013-06-231-6/+11
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-06-201-2/+28
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| * Added renaming of wires and cells to "rename" commandClifford Wolf2013-06-191-2/+28
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