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* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-281-1/+45
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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-261-10/+10
| | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* Ensure \A_SIGNED is never used with $shiftxXiretza2020-08-181-0/+4
| | | | | It has no effect on the output ($shiftx doesn't perform any sign extension whatsoever), so an attempt to use it should be caught early.
* Merge pull request #2201 from YosysHQ/fix_test_cell_ilangclairexen2020-06-301-2/+2
|\ | | | | Use ID macro to fix assertion
| * Use ID macro to fix assertionMiodrag Milanovic2020-06-291-2/+2
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* | test_cell: don't generate directional shifts with \B_SIGNED=1Xiretza2020-06-281-0/+4
|/ | | | | This was made an explicit error in e97e33d, "kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.".
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
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* Add flooring division operatorXiretza2020-05-281-1/+2
| | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* Add flooring modulo operatorXiretza2020-05-281-1/+2
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-97/+97
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* kernel: use more ID::*Eddie Hung2020-04-021-38/+38
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* More use of IdString::in()Eddie Hung2019-08-151-2/+2
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* substr() -> compare()Eddie Hung2019-08-071-1/+1
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* RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-17/+17
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* stoi -> atoiEddie Hung2019-08-071-2/+2
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* Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-2/+2
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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-2/+0
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* Removed $predict againClifford Wolf2016-08-281-1/+0
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* Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()Clifford Wolf2016-07-251-1/+1
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* Improvements in CellEdgesDatabaseClifford Wolf2016-07-241-3/+33
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* Added CellEdgesDatabase APIClifford Wolf2016-07-241-0/+96
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* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-1/+1
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* Added basic support for $expect cellsClifford Wolf2016-07-131-0/+2
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* Improved support for $sop cellsClifford Wolf2016-06-171-2/+38
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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
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* Added "test_cell -noeval"Clifford Wolf2015-09-251-1/+10
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* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-1/+1
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* Renamed "aig" to "aigmap"Clifford Wolf2015-06-101-4/+4
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* Fixed cellaigs port extendingClifford Wolf2015-06-101-0/+7
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* Replaced ezDefaultSAT with ezSatPtrClifford Wolf2015-02-211-5/+5
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* Added "test_cell -muxdiv"Clifford Wolf2014-12-251-2/+18
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* Added "test_cell -w" featureClifford Wolf2014-12-251-18/+39
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* Fixed typo in test_cellClifford Wolf2014-10-181-1/+1
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-36/+36
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* namespace YosysClifford Wolf2014-09-271-0/+4
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* Added $lcu cell typeClifford Wolf2014-09-081-1/+26
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* Added "$fa" cell typeClifford Wolf2014-09-081-0/+31
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* Added "test_cell -const"Clifford Wolf2014-09-081-2/+45
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* Added "test_cell -nosat"Clifford Wolf2014-09-071-59/+73
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* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-061-1/+1
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* Added $macc SAT modelClifford Wolf2014-09-061-5/+6
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* Added $macc cell typeClifford Wolf2014-09-061-2/+53
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* Added "test_cell -script"Clifford Wolf2014-09-061-1/+8
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* Removed $bu0 cell typeClifford Wolf2014-09-041-1/+0
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* Fixed "test_cells -vlog"Clifford Wolf2014-09-031-4/+6
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* Improvements in "test_cell -vlog"Clifford Wolf2014-09-021-3/+8
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* Added test_cell -vlogClifford Wolf2014-09-021-2/+79
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* Added SAT testing to test_cell eval stageClifford Wolf2014-09-021-1/+89
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