Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Merge branch 'eddie/xilinx_srl' into xaig_arrival | Eddie Hung | 2019-08-28 | 1 | -174/+5 |
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| * | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-28 | 4 | -88/+456 |
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| * | | Actually, there might not be any harm in updating sigmap... | Eddie Hung | 2019-08-22 | 1 | -3/+1 |
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| * | | Add comment as per @cliffordwolf | Eddie Hung | 2019-08-22 | 1 | -0/+11 |
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| * | | Revert "Try way that doesn't involve creating a new wire" | Eddie Hung | 2019-08-22 | 1 | -15/+10 |
| | | | | | | | | | | | | This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b. | ||||
| * | | Try way that doesn't involve creating a new wire | Eddie Hung | 2019-08-22 | 1 | -10/+15 |
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| * | | If d_bit already in sigbit_chain_next, create extra wire | Eddie Hung | 2019-08-22 | 1 | -3/+6 |
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| * | | Remove `shregmap -tech xilinx` additions | Eddie Hung | 2019-08-22 | 1 | -189/+8 |
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* | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-28 | 4 | -88/+456 |
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| * | | Fix typo | Clifford Wolf | 2019-08-28 | 1 | -2/+2 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Add "paramap" pass | Clifford Wolf | 2019-08-28 | 1 | -67/+118 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | improve clkbuf_inhibit propagation upwards through hierarchy | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+12 |
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| * | | clkbufmap to only check clkbuf_inhibit if no selection given | Eddie Hung | 2019-08-23 | 1 | -5/+18 |
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| * | | Review comment from @cliffordwolf | Eddie Hung | 2019-08-23 | 1 | -1/+2 |
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| * | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 20 | -311/+350 |
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| * | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-16 | 26 | -1135/+1130 |
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| * | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 2 | -28/+9 |
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| * | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 2 | -29/+4 |
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| * | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 3 | -20/+356 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | ||||
* | | | | Cleanup | Eddie Hung | 2019-08-23 | 1 | -130/+59 |
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* | | | | Merge branch 'eddie/fix_techmap' into xaig_arrival | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| * | | | Grammar | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| * | | | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 |
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* | | | | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 |
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* | | | | Remove sequential extension | Eddie Hung | 2019-08-20 | 1 | -68/+20 |
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* | | | | retime_mode -> dff_mode | Eddie Hung | 2019-08-20 | 1 | -7/+7 |
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* | | | | Fix use of {CLK,EN}_POLARITY, also add a FIXME | Eddie Hung | 2019-08-20 | 1 | -65/+13 |
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* | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 1 | -6/+6 |
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| * | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 1 | -43/+80 |
| |\ \ \ | | | | | | | | | | | Refactor abc9 to use port attributes, not module attributes | ||||
| | * | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 1 | -6/+6 |
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* | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-19 | 1 | -1/+1 |
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| * | | | | Fix typo | Eddie Hung | 2019-08-19 | 1 | -1/+1 |
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* | | | | | Remove debug | Eddie Hung | 2019-08-19 | 1 | -1/+1 |
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* | | | | | Add (* abc_arrival *) attribute | Eddie Hung | 2019-08-19 | 1 | -1/+1 |
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* | | | | | Move from cell attr to module attr | Eddie Hung | 2019-08-19 | 1 | -24/+64 |
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* | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-19 | 20 | -263/+263 |
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| * | | | | Merge pull request #1283 from YosysHQ/clifford/fix1255 | Clifford Wolf | 2019-08-17 | 1 | -1/+1 |
| |\ \ \ \ | | | | | | | | | | | | | Fix various NDEBUG compiler warnings | ||||
| | * \ \ \ | Merge branch 'master' into clifford/fix1255 | Clifford Wolf | 2019-08-15 | 1 | -2/+2 |
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| | * | | | | | Fix various NDEBUG compiler warnings, closes #1255 | Clifford Wolf | 2019-08-13 | 1 | -1/+1 |
| | | |_|/ / | | |/| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | | Merge pull request #1300 from YosysHQ/eddie/cleanup2 | Clifford Wolf | 2019-08-17 | 20 | -262/+262 |
| |\ \ \ \ \ | | |_|_|_|/ | |/| | | | | Use ID::{A,B,Y,keep,blackbox,whitebox} instead of ID() | ||||
| | * | | | | Use ID::keep more liberally too | Eddie Hung | 2019-08-15 | 4 | -9/+9 |
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| | * | | | | Use more ID::{A,B,Y,blackbox,whitebox} | Eddie Hung | 2019-08-15 | 20 | -253/+253 |
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* | | | | | | Use attributes instead of params | Eddie Hung | 2019-08-19 | 1 | -11/+25 |
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* | | | | | | Set abc_flop and use it in toposort | Eddie Hung | 2019-08-19 | 1 | -31/+51 |
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* | | | | | | Merge branch 'eddie/abc9_refactor' into xaig_dff | Eddie Hung | 2019-08-16 | 27 | -1267/+1501 |
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| * | | | | | Use ID() | Eddie Hung | 2019-08-16 | 1 | -3/+3 |
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| * | | | | | Compute abc_scc_break and move CI/CO outside of each abc9 | Eddie Hung | 2019-08-16 | 1 | -43/+80 |
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| * | | | | Merge pull request #1302 from mmicko/dfflibmap_regression | Clifford Wolf | 2019-08-16 | 2 | -10/+10 |
| |\ \ \ \ | | | | | | | | | | | | | DFFLIBMAP pass regression fix | ||||
| | * | | | | Regression in abc9 | Miodrag Milanovic | 2019-08-16 | 1 | -1/+1 |
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| | * | | | | Just needed IDs to be IdString | Miodrag Milanovic | 2019-08-16 | 1 | -9/+9 |
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